High-speed video display system

DETAILED DESCRIPTION The invention may be incorporated into a graphics sub-system including frame memory and a video digital-to-analog converter (VDAC).
The VDAC includes a clock input terminal for receiving the output of a high speed oscillator, as a pixel clock signal.
The pixel clock signal controls the application of each pixel's data to circuitry for generating the output to the display.
A divide-down circuit is also provided in the VDAC to generate an output clock signal based on the pixel clock signal.
The output clock signal controls the system video controller, which in turn controls the serial output of the frame memory.
The VDAC also has a second clock input for receiving a clock input generated by the video controller, responsive to which pixel data from the frame memory is latched into the VDAC.
Two-stage latching is provided within the VDAC, so that the pixel clock controls the application of the contents of the first latch to the VDAC output.
Accordingly, the loading of data into the VDAC may be done independently from the clocking out of the data from the VDAC.
The pixel clock frequency is therefore not limited by the propagation delay through the video controller, increasing the pixel display rate and enabling the driving of higher resolution displays.