DETAILED DESCRIPTION The present invention relates to a method and apparatus for performing data operations using a low hold time statisized dynamic flip-flop.
The present invention also relates to a method and apparatus for performing scan operations using a low hold time statisized dynamic flip-flop.
Turning now to the present invention, at the start of an evaluation phase, the value of a data input is immediately latched using a feedback stage so that the hold time needed to keep the data input constant is reduced.
More particularly, the present invention uses a dynamic stage that feeds back onto a setup node to hold the value of a data input during an evaluation phase of the dynamic stage regardless of whether the data input transitions after the start of the evaluation phase.
Further, during a precharge phase of the dynamic stage, the feedback is disabled to enable data on the setup node to be setup.
FIG.
6a shows an exemplary circuit schematic of a flip-flop header block (180) in accordance with an embodiment of the present invention.
The flip-flop header block (180) provides control signals to a flip-flop core block (200) (shown in FIG.
6b), where the control signals are dependent on input signals to the flip-flop header block (180).
Essentially, the flip-flop header block (180) indicates to the flip-flop core block (200) (shown in FIG.
6b), via the control signals, what mode to operate in.
The flip-flop header block (180) shown in FIG.
6a inputs a scan enable signal, SE, and a global clock signal, CLK.
SE serves as an input to a first inverter (182), which, in turn, outputs to both a first input of a first NOR gate (184) and a first input of a NAND gate (186).
CLK serves as an input to a second inverter (188), which, in turn, outputs to both a third inverter (190) and to a second input of the NAND gate (186).
The third inverter (190) outputs to both a second input of the first NOR gate (184) and an output, CK, of the flip-flop header block (180).
The NAND gate (186) outputs to a fourth inverter (192), which, in turn, outputs to both a fifth inverter (194) and another output, CK_2 (discussed below), of the flip-flop header block (180)
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