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Home Coded Low-power-reference-buffer-circuit-utilizing-switched-capacitors

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 Low power reference buffer circuit utilizing switched capacitors

Details
Inventors: Thilenius, Stephen C;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: JeanPierre; Peguy
Assistant Examiner:
Attorney, Agent or Firm: Pillsbury Winthrop LLP

A reference buffer circuit includes a first switched capacitor selectively coupled to a first node that receives a reference voltage from a buffer device connected to the first node. A second switched capacitor is selectively coupled to a voltage source to receive a charging voltage from the voltage source. A first switch is coupled to the first switched capacitor to switch communication of the first switched capacitor between the first node and a second node. And, a second switch is coupled to the second switched capacitor to switch communication of the second switched capacitor between the voltage source and the first node, wherein the second switched capacitor delivers the charging voltage to the first switched capacitor.

DETAILED DESCRIPTION Reference in the specification to "one embodiment", "an embodiment", or "another embodiment" of the present invention means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention.
Thus, the appearances of the phrase "in one embodiment" or "according to an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
Likewise, appearances of the phrase "in another embodiment" or "according to another embodiment" appearing in various places throughout the specification are not necessarily referring to different embodiments.
FIG.
1A illustrates a reference buffer circuit according to an embodiment of the present invention.
The reference buffer circuit 100 includes a buffer device 110, a voltage source 120, a first switch 130, a second switch 140, a first switched capacitor 150, a second switched capacitor 160, a first node 180, and a second node 190.
The buffer device 110 is coupled to the first node 180 to provide a reference voltage to the first switched capacitor 150.
The voltage source 120 provides a charging voltage to the second switched capacitor 160.
The first switch 130 is coupled to the first switched capacitor 150 to switch between the first node 180 and the second node 190.
The second switch 140 is coupled to the second switched capacitor 160 to switch between the voltage source 120 and the first node 180.
The first switched capacitor 150 receives the reference voltage from the buffer device 110.
The second switched capacitor 160 delivers the charging voltage to the first switched capacitor 150.
According to an embodiment of the present invention, the reference buffer circuit 100 may further include a third switch 170 coupled to the second switched capacitor 160 to switch between the second voltage source 125 and a reference potential.
The reference potential may be a ground potential.
In an embodiment of the present invention, referring to FIG



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