Vertical deflection circuit for a cathode-ray tube having a vertical image-position adjustment circuit |
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Windshield wiper system |
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Method to control stops of an intermittently operating driving motor |
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Rearview mirror actuating device |
| OF A PREFERRED EMBODIMENT OF THE PRESENT INVENTION Referring first to FIG. 1, a mirror actuating ... |
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Power memory seat and mirror control system |
| OF A PREFERRED EMBODIMENT With reference now to drawing FIGS. 1 and 2, there is shown in FIG. 1 a ... |
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Microstepping of an unipolar stepping motor |
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Integrated interface circuit between a television receiver and its peritelevision connector |
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Method and apparatus for automatically adjusting noise immunity of an integrated circuit
| Details |
Inventors: Allen, David Howard; Stasiak, Daniel Lawrence;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Wells; Kenneth B.
Assistant Examiner: Cox; Cassandra
Attorney, Agent or Firm: Felsman, Bradley, Vaden, Gunter & Dillon
An integrated circuit having an apparatus for automatically adjusting noise immunity is disclosed. The integrated circuit includes multiple functional logic circuits, a clock generator, a group of noise monitor circuits, and a control logic circuit. The clock generator generates a clock signal to all these circuits. The noise monitor circuits are utilized to detect noise occurring in the integrated circuit. In response to any noise detected by the noise monitor circuits, the control logic circuit decreases the speed of the clock signal sent to all the circuits, especially the functional logic circuits, via a slow down signal to the clock generator. Alternatively, the control logic circuit can inform the functional logic circuits via a noise alert signal to increase the noise immunity of certain noise sensitive circuits within the functional logic circuits. |
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DETAILED DESCRIPTION In accordance with a preferred embodiment of the present invention, a noise-immune integrated circuit that is capable of automatically adapting to environmental changes includes multiple functional logic circuits, a clock generator, a group of noise monitor circuits, and a control logic circuit. The clock generator generates a clock signal to all these circuits. The noise monitor circuits are utilized to detect noise occurring in the integrated circuit. In response to any noise detected by the noise monitor circuits, the control logic circuit decreases the speed of the clock signal sent to all the circuits, especially the functional logic circuits, via a slow down signal to the clock generator. Alternatively, the control logic circuit can inform the functional logic circuits via a noise alert signal to increase the noise immunity of certain noise sensitive circuits within the functional logic circuits. All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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