 Dynamic voltage reference which compensates for process variations |
| The present invention concerns a dynamic voltage reference circuit for generating one or more ... |
|
| Amplifier arrangement and method and voltage controlled amplifier and method |
| It is, accordingly, an object of the present invention to provide an electronic amplifier ... |
|
| Active noise and vibration control system |
| It is, therefore, an object of the present invention to provide an improved system for controlling ... |
|
| Method and apparatus for microwave predistorter linearizer with electronic tuning |
| In one aspect of the invention, a predistorter linearizer for use with a radio frequency amplifier ... |
|
| Spectral shaping of circuit errors in digital-to-analog converters |
| The present invention is a hardware-efficient DAC topology that can be used to achieve a variety of ... |
|
| Method and apparatus for mismatched shaping of an oversampled converter |
| An embodiment of the present invention is directed to a method and apparatus for spectrally shaping ... |
|
| Spectral shaping dynamic encoder for a DAC |
| A tree-structured dynamic encoder in accordance with the invention generates an N-bit encoder ... |
|
| Gauge for remotely indicating the pressure of a subterranean formation |
| Referring to the drawings and first to FIG. 1, the portion of the gauge which is lowered into a ... |
|
| Down hole apparatus for sensing and storing values of physical parameters |
| It is a primary object of this invention to provide a subsurface, self-contained, self-powered, ... |
|
|
Method and apparatus for calibrating a multi-bit delta-sigma modular
| Details |
Inventors: Thompson, Charles D.; Bernadas, Salvador R.; van Bavel, Nicholas R.; Swanson, Eric J.;
Assignee: Crystal Semiconductor, Inc. (Austin, TX)
Primary Examiner: Williams; Howard L.
Assistant Examiner:
Attorney, Agent or Firm: Howison; Gregory M.
A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input. |
|
DETAILED DESCRIPTION The present invention disclosed and claimed herein comprises a method and apparatus for compensating for non-linearities in an analog-to-digital converter having a multi-level output delta-sigma modulator.
The delta-sigma modulator is an m-level output with m greater than two, the output of which is input to a digital filter.
The digital filter operates in accordance with filter coefficients stored in a memory.
The memory is also operable to store non-linearity compensation parameters.
The operation of the digital filter is controlled to compensate for the non-linearities that exist in the delta-sigma modulator during the operation of the digital filter.
In another aspect of the present invention, the digital filter is driven with the m-level output of the delta-sigma modulator.
The compensation device is operable to compensate m-2 of the m-levels that are utilized to drive the digital filter in accordance with the stored non-linearity parameters.
In the preferred embodiment, the value of m is equal to three.
In yet another aspect of the present invention, the multi-level output of the delta-sigma modulator is comprised of a -1 level, a "do nothing" level and a +1 level.
The filter is comprised of first and second processors for processing the +1 level and -1 level, respectively, each of the processors for receiving the stored filter coefficients and providing a set of accumulated filter coefficients that are accumulated as a function of the associated level being output from the delta-sigma analog modulator.
A summation device is operable to receive the output of the first and second processors and sum the difference therebetween.
The compensation device compensates the output of one of the first and second processors in accordance with the stored non-linearity compensation parameters prior to summation with the summation device.
In a further aspect of the present invention, a calibration device is provided for determining the non-linearity parameters in response to receiving a calibration signal
|
| Related patents |
|
|
Digital to analog converter for sigma delta modulator
In accordance with the present invention, a digital to analog converter is provided which substantially eliminates or reduces disadvantages and problems associated with ...
|
|
|
Digital-to-analog converter with digital linearity correction
In accordance with a basic aspect of the present invention, there is provided a method of operating a digital-to-analog converter. The method includes the steps of: ...
|
|
|
Pulse generating circuit for dynamic random access memory device
Accordingly, the present invention is directed to a pulse generating circuit for dynamic random access memory device that substantially obviates one or more of problems ...
|
|
|
Low voltage latch with uniform stack height
According to one embodiment of the invention, latch components are comprised of low threshold transistors. In addition, according to one embodiment of the invention, to ...
|
|
|
Remote controlled thermostat
OF THE PREFERRED EMBODIMENT The present invention is a method and apparatus for remotely adjusting the temperature of a building. Referring to FIG. 1, the apparatus ...
|
|
|
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
Description:...
|
|
|
A/D signal conversion based on a comparison of voltage-divided signals
FIG. 1 is a block diagram of portions of flash analog-to-digital (A/D) converter 1 according to some embodiments. A/D converter 1 includes resistor string 10, which in ...
|
|
|
Rectangular wave pulse generators
The circuit illustrated in FIG. 1 comprises an oscillator 10 which provides a periodic output signal (waveform (a) in FIGS. 2A and 2B) which is stable in frequency, as ...
|
|
|
Method of making master slice type integrated circuit device
It is hence a primary object of this invention to present master slice type integrated circuit device and manufacturing method thereof capable of solving the above-...
|
|
|
Circuit and method for generating a clock signal
In accordance with the teachings of the present invention, a circuit and method for generating a clock signal are provided. The clock generator circuit includes a ...
|
|
|
Coded 
