Method of synchronizing two binary trains

DETAILED DESCRIPTION To this end, the invention provides a method of synchronizing two binary trains in order to switch from the first train to the second, wherein a synchronization range is used which extends between a first position in a buffer memory storing the train which is directed to the output and for which reading follows writing by one bit period, to a second position where reading precedes writing by one bit period.
More precisely, the invention provides a method comprising the following steps: comparing phases between the clocks associated with the two trains by means of a phase comparator, said comparison taking place in a state where reading follows or precedes writing by one position in the buffer memory for the train which is directed to the output; seeking synchronization by inhibiting the second train or else passing to the second position for reading relative to writing by modifying the phase comparator and returning to the preceding step; switching from the first train to the second train if synchronization is obtained after N shifts in the buffer memory; and switching from the first train to the second train if synchronization is not found after searching for a determined length of time.
The invention also provides apparatus for implementing the method, said apparatus comprising two buffer memories having N positions each and in which the two trains are stored, two write inhibit devices in said memories, a synchronization logic circuit, a phase lock loop which includes a phase comparator, a low pass filter, a voltage controlled oscillator, and a divide-by-N circuit fed back to a first input of the phase comparator, the second input of the comparator being connected via a first switch to one of the clocks associated with the two trains after passing through two divide-by-N circuits.
It also enables bit-by-bit comparison of the binary trains by means of an exclusive-OR gate which receives the binary trains read from the two buffer memories and which is connected to the synchronization logic circuit