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Multistep analog-to-digital converter with successive approximation register circuit for least significant bit resolution
| Details |
Inventors: Mayes, Michael K.; Chin, Sing W.;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: Logan; Sharon D.
Assistant Examiner:
Attorney, Agent or Firm: Flehr, Hohbach, Test, Albritton & Herbert
An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value. |
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DETAILED DESCRIPTION In summary, the present invention is used in an analog-to-digital converter (ADC) having at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages.
The ADC furthermore includes an embedded memory for storing a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage.
Each of the aforementioned comparator circuits has two input nodes, one of which receives a reference voltage from the resistance ladder and the other of which receives a voltage derived from the input voltage.
During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages.
The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage.
In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value.
In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.
The first two conversion cycles generate a ten-bit digital value representing the input voltage.
In a third conversion cycle, two additional bits of resolution are added to the conversion value using a "successive approximation" circuit.
Furthermore, the third conversion cycle also corrects errors of up to .
+-.
6 LSB in the first ten bits of the Fout value
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