Pipelined analog-to-digital converter (ADC) with 3-bit ADC and endpoint correction

DETAILED DESCRIPTION In accordance with the presently claimed invention, a pipelined analog-to-digital converter (ADC) is provided in which one less pipeline stage is needed while the output ADC stage has its resolution increased by one bit, thereby advantageously providing for decreased circuit area, lower power consumption and endpoint correction, with minimal additional circuitry.
In accordance with one embodiment of the presently claimed invention, a pipelined analog-to-digital converter (ADC) includes a plurality of pipeline stages coupled in series and including a first pipeline stage, at least one intermediate pipeline stage and a last pipeline stage, each of which provides M bits of resolution for an N-bit digital output signal corresponding to an analog input signal, and a final ADC.
The first pipeline stage is responsive to the analog input signal by providing a first analog residue signal and a first digital signal with M+1 bits corresponding to M+1 most significant bits (MSBs) of the N-bit digital output signal.
Each of the at least one intermediate pipeline stage is responsive to a prior analog residue signal by providing a subsequent analog residue signal and an intermediate digital signal with M+1 bits corresponding to M+1 less significant intermediate bits of the N-bit digital output signal.
The last pipeline stage is responsive to a last subsequent analog residue signal by providing a final analog residue signal and a last digital signal with M+1 bits corresponding to M+1 lesser significant intermediate bits of the N-bit digital output signal.
The final ADC is coupled to the last pipeline stage and responsive to the final analog residue signal by providing a final digital signal with 2M+1 bits corresponding to 2M+1 least significant bits (LSBs) of the N-bit digital output signal.
In accordance with another embodiment of the presently claimed invention, a pipelined analog-to-digital converter (ADC) includes pipeline means and final ADC means.
First pipeline means is for receiving an analog input signal and in response thereto generating a first analog residue signal and a first digital signal with M+1 bits corresponding to M+1 most significant bits (MSBs) of an N-bit digital output signal