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Home Coded Re-synchronization-of-independently-clocked-audio-streams-by-dynamically-switching-among-3-ratios-for-sampling-rate-conversion

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Details
Inventors: Lin, Tao;
Assignee: NeoMagic Corp. (Santa Clara, CA)
Primary Examiner: Tokar; Michael
Assistant Examiner: JeanPierre; Peguy
Attorney, Agent or Firm: Auvinen; Stuart T.

A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P. The accumulator value is used to select one group of L coefficients in a set of P groups to apply to a convolution FIR filter that generates the output sample from L input samples stored from the FIFO in a shift register.

DETAILED DESCRIPTION A sample-rate converter has an input stream of samples representing audio intensities at points in time.
The input stream plays the samples at an input rate of an input clock.
An output stream of samples representing audio intensities at points in time is for playing the samples at an output rate of an output clock.
A buffer receives the samples from the input stream in response to the input clock.
A derived-clock generator is coupled to the output clock.
It generates a derived clock from the output clock.
A filter stage is coupled to receive samples from the buffer in response to a derived clock.
It converts samples read from the buffer at a derived rate of the derived clock to output samples output at the output rate.
A target indicator is coupled to the input clock and coupled to the derived clock.
It indicates when the buffer contains a target number of samples, and when the buffer contains less than the target or more than the target number of samples.
The derived-clock generator generates the derived clock with a nominal frequency when the target indicator indicates that the buffer contains the target number of samples.
However, the derived-clock generator generates the derived clock with an accelerated frequency when the target indicator indicates that the buffer contains more than the target number of samples.
Also, the derived-clock generator generates the derived clock with a slowed frequency when the target indicator indicates that the buffer contains less than the target number of samples.
Thus the derived clock that reads the buffer is accelerated and slowed in response to a number of samples stored in the buffer.
In further aspects the buffer is a first-in-first-out FIFO.
A conversion ratio of the input rate to the output rate is represented by Q/P.
The nominal frequency is Q/P times the output rate.
The accelerated frequency is (Q+x)/P times the output rate and the slowed frequency is (Q-x)/P times the output rate, where x is a small whole number while Q is a whole number greater than 100



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