Character/vector controller for stroke written CRT displays

DETAILED DESCRIPTION We claim: 1.
A system for drawing characters on the face of a cathode ray tube by developing respective X and Y deflection signals which collectively define a vector of selected length and polar angle, comprising: a microprocessor providing a digital addressing output assigned to each of a plurality of characters to be drawn on the face of the cathode ray tube; a first read-only memory means receiving said microprocessor addressing outputs and outputting a sequence of digital data bytes sequentially definitive of contiguous vectors defining that character, each said vector defining byte being defined by bits definitive of straight-line segment lengths and angles of contiguous vectors defining that character including bits defining the segment angle and a video on-off bit; means for selectively adding to said bits defining each segment angle of a character, to obtain a summation angle, a character rotation angle outputted from said microprocessor; means addressing a second read-only memory means to output respective sine and cosine functions of said summation angle outputted by said adding means; means for selectively applying said sine and cosine functions from said second read-only means as respective inputs to first and second variable rate integrators; means responsive to said straight-line segment length defining bits outputted from said first read-only memory means to output a timing signal proportional to the length of that segment; means for enabling said integrators for the time duration of said timing signal; and means for enabling the beam of said cathode ray tube in response to said video on-off signal outputted from said first read-only memory means, wherein said integrators directly generate deflection signals.
2.
A system as defined in claim 1 further including first and second digital logic means, said first digital logic means responsive to predetermined bit outputs from said adder to develop polarity definitive outputs respectively defining the polarity of sine and cosine functions of the angle defined by the output of said adder, and said second logic means responsive to the output of said first digital logic means to apply said sine and cosine definitive signals during periods of time defined by said timing signal to said variable rate integrators with respective polarities as defined by the quadrant within which the angle defined by said adder output lies