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 Semiconductor intergrated circuit device

Details
Inventors: Tomioka, Ichiro; Sakashita, Kazuhiro; Kishida, Satoru; Hanibuchi, Toshiaki; Arakawa, Takahiko;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Eisenzopf; Reinhard J.
Assistant Examiner: Burns; W.
Attorney, Agent or Firm: Nixon & Vanderhyde

A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

DETAILED DESCRIPTION An object of the present invention is to provide a semiconductor integrated circuit device which can eliminate the above-mentioned drawbacks and disadvantages and which can be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.
In order to achieve these and other objects, there is provided according to one aspect of the present invention a semiconductor integrated circuit device comprising a scan register provided between circuit blocks to be tested for outputting input data as is in a through state between input and output terminals at ordinary operation time and holding and outputting input data at testing time, and a gate circuit connected to the output terminal of the scan register for outputting a predetermined fixed value at ordinary operation time and in a test mode at testing time to control the output of the test data by the gate control input.
In this aspect of the present invention, the predetermined fixed value can be applied to a circuit block to be tested at scanning time irrespective of the output of the other circuit block and test data can be applied at a predetermined timing thereto at testing time by the gate circuit inserted to the output of the scan register to prevent the data applied to the circuit block to be tested from altering in case of switching the mode at testing time.
In order to achieve these and other objects, there is provided according to another aspect of the present invention a semiconductor integrated circuit device comprising a scan register provided between circuit blocks to be tested and having first and second latches for outputting input data as it is in a through state at least between an input terminal, a gate circuit connected to the output terminal of the scan register for outputting a predetermined fixed value at ordinary operation time and in a test mode at testing time to control the output of the test data by the gate control input, and a latch circuit for outputting the output data of the scan register before scanning operation to control the output of the test data by the control input



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