Systolic computational array

DETAILED DESCRIPTION The present invention provides a systolic computational array including two shift registers.
Some, but not all, of the stages of each shift register are adapted to provide the value contained therein to two multiply-accumulate devices.
In this manner 2N-1 summations may be performed using two N stage shift registers.
Thus fewer shift register stages are required, leading to a proportionate space saving.
Additionally the system of the present invention requires less time to calculate a correlation because values may be loaded into consecutive shift register stages and all multiply-accumulate devices operate during every cycle.