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Transmitter circuit comprising timing deskewing means
| Details |
Inventors: Deas, Alexander Roger; Atyunin, Vasily Grigorievich; Abrosimov, Igor Anatolievich;
Assignee: Acuid Corporation Limited (Guernsey, GB)
Primary Examiner: Tokar; Michael
Assistant Examiner: Tran; Anh
Attorney, Agent or Firm:
The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew. The present invention allows to reduce the skew of signals at the end of a transmission line so as to compensate for the effects of cross-talk and various signal reflections, settling time influence, or other kind of inter-symbol interference like frequency dependent line resistance due to skin effect and provide thereby a high performance transmission means for high speed transmission of digital data. |
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DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a de-skewing means for compensating skew caused by inter-symbol interference and cross-talk influence in high speed communication systems.
The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements.
Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments.
Therefore, the present invention is not intended to be limited to the particular embodiment shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
In FIG.
1 a driving circuit according to the first embodiment of the present invention is shown.
The circuit comprises a driver 13 for driving a transmission line, a device for storing information transferred during a preselected period of time, which can be implemented as shift register 11, and a deskewing means.
The deskewing means consists of flip-flop 12, the clock input of which is connected to the vernier device 15, wherein the data input of the flip-flop is supplied with the most recent data bit from the shift register 11.
The vernier 15 is controlled by a control unit, which can be simply a look-up table implemented as SRAM 14.
The look-up table is used to store the values or parameters relating to the previous signal patterns.
The input data for the control unit are the data from shift register 11 containing information on the transferred data.
The circuit operates as follows.
Assume the incoming signal is supplied to shift register 11.
Depending on the historical data pattern in the data line, control unit 14 generates an appropriate code to the vernier 15.
Vernier 15 delays input clock signal for flip-flop 12 according to this code, thereby flip-flop 12 clocks the current input data fed therein with a respective timing adjustment
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Control Computers 
