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Ultra-modular processor in lattice topology
| Details |
Inventors: McNeil, Donald H.;
Assignee:
Primary Examiner: Perveen; Rehana
Assistant Examiner: Patel; Nimesh
Attorney, Agent or Firm: Lowe Hauptman & Berner, LLP Bindseil; James J.
A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single miniaturized packages, e.g., Compact Flash, each with a full function processor (CPU), a unique resident operating system, and dedicated applications. Internally accessed data and internal applications are invisible to the outside. A host external bus connection handles mass storage volumes, which support file-level data transfers. A software-latticed network of MOTEs defines a network element for a larger system. Multiple MOTEs operate concurrently in a non-hierarchical (ladder) interconnection using a circulating message exchange protocol with concurrent operation of the MOTEs. MOTE resident software mirrors inter-modular processor architecture, permitting support of concurrent processes with an exchange of messages circulated on a logical (software) bus. Each network MOTE is dedicated to a specific system function. Data and software programs can be kept secure against unauthorized access. |
|
DETAILED DESCRIPTION The objects of the present invention are realized in miniaturized self-contained hot-pluggable and physically dismountable computing system herein called a Modular Operating Topology Element (MOTE) typically imbedded in package similar in size to a Compact Flash.
TM.
(CF) unit or a PC Card, SmartMedia.
TM.
Memory Card, Multi-Media Card.
TM.
(MMC) or other such package, although somewhat larger packaging may also be used in order to accommodate more powerful computer circuits and/or multiple peripheral I/O ports.
Further, the objectives of the present invention are realized in an array of such miniaturized self-contained computing systems and a method for logically interconnecting and managing the operation of such array as a smart lattice network.
Each MOTE, as for example, a 50 pin CF-sized package, has imbedded within it a programmable processor (CPU) with operating capabilities at least equivalent in memory addressing and interrupt handling facility to a Motorola.
RTM.
68xxx processor.
An internal hardware bus is connected to the CPU.
Non-volatile random access memory (RAM) is connected to the hardware bus and provides working memory and mass storage memory for the device.
Non-volatile read only memory (ROM) is also connected to the internal hardware bus and contains the dedicated operating system for the CPU, the software drivers for I/O attached to the device, and (optionally) application program code and data.
A battery-backed real time clock-calendar unit is connected to the CPU through the hardware bus.
Exception control circuits attached to the internal hardware bus provide for program-settable interval timer interrupts and watchdog timer interrupts to the CPU.
Host interface I/O circuits connect the internal hardware bus to an external bus port for communication with an external computing system (host) hardware bus, e.
g.
, PCMCIA bus, CF.
TM.
bus, SmartMedia.
TM.
bus, MMC.
TM.
bus, USB, IEEE 1394 (Firewire.
RTM.
) or other.
The MOTE device may also optionally include I/O interface circuits for connection to one or more peripheral devices external to itself, e
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Control Computers 
