Wafer processing cassette

DETAILED DESCRIPTION The general purpose of the present invention is to provide a wafer cassette for processing of integrated circuit wafers such as silicon wafers or the like which provides low-profile structure for on-center processing of the cassette by advanced generation integrated circuit robotic wafer processing equipment.
The wafer processing cassette includes an integral structure of the cassette with strategically located components of the H-bar end and geometrically configured reinforced wafer dividers providing for open, non-restricted areas for integrated circuit processing.
Also, the wafer cassette is of an extremely low profile and of minimal weight, which provides for a lower unit cost to the integrated circuit processor.
According to one embodiment of the present invention there is provided a wafer cassette for processing of integrated circuit wafers, such as silicon wafers including a substantially rectangular configured H-bar front end including a ramped upper portion, a rectangular lower portion, and a partial cylindrical reinforcing rod running the longitudinal length of the center of the H-bar end, upper edge members having locating pins and holes, forward and rearward vertical support bars in support of horizontal structure supports in the area of the locating pins and holes, a plurality of reinforced wafer dividers having geometrically shaped teeth, the reinforced exterior portion being more round in shape than the interior portion of the teeth, opposing horizontal longitudinal structural supports secured to the front H-bar support and a rear end at a upper and lower mid portion of the dividers, or mid portion of the dividers, and angled rounded opposing sides above a reinforced bottom edge for perimeter contact, whereby the open H-bar end and downward arch rear end provide for maximum open end areas.
The open dividers with geometrically configured teeth of dual rounded faces provide for maximum surface area for processing functions thereby providing a fully functional strategically located low-profile least weight wafer cassette of structural integrity for on-center processing of integrated circuit wafers