Ramp release and reset circuit for a three phase voltage regulator

DETAILED DESCRIPTION It is the main object of the present invention to provide a ramp release and reset circuit which is substantially unaffected by distortion in the generating sinewave.
It is another object of the present invention to provide an improved ramp release and reset circuit which is a logic circuit based on a predetermined logical function.
It is another object of the present invention to provide a ramp release and reset circuit in which the ramp release and reset timing pulses are generated at the crossover point between the sinewave and an offset voltage where the sinewave is only approaching the zero crossover line.
Briefly, an improved ramp release and reset circuit is provided for a three phase voltage regulation system, which includes a pair of comparators for each phase of the three phase input to the system for generating two 180.
degree.
out of phase timing pulses for each phase.
A voltage offset means is included associated with each comparator, which raises the comparator switching point above the zero crossover point on each phase input.
A logical circuit is driven by the predetermined combination of the 180.
degree.
out of phase timing pulses from each of the pair of comparators to produce ramp timing pulses at each output of the logic circuit in accordance with the logic in the logical circuit.
A linear ramp generator, one associated with each of the logical circuit outputs, generates linear ramps released and reset by the beginning and end, respectively, of each of said ramp timing pulses.