Data shifting circuit capable of an original data width rotation and a double data width rotation

DETAILED DESCRIPTION This invention concerns a data shifting circuit of a central processing unit e.
g.
for use in a computer.
The present invention realizes a data shifting circuit, of a central processing unit, capable of shifting data both by an original shift width and by a double shift width, with neither a significantly larger hardware volume nor an increase in data delay.
The present invention configures a data shifting circuit of a central processing unit comprising a shifter, a register group and a data controller.
The shifter may shift data by the bit number of a double shift width.
The double shift width is twice as wide as an original shift width.
The register group comprises a plurality of registers each storing data to be shifted.
The data controller, inserted between the register group and the shifter, receives a register number specification signal designating a register and selectively receives a double width shift request signal requesting data be shifted by the double shift width.
When the data shifting circuit needs to shift data by the double shift width, the data controller inputs data stored in the specified register and data stored in another register associated with the specified register in a predetermined relation respectively to the most significant bits and the least significant bits of the shifter.