Apparatus for detecting undefined states of a finite state machine (FSM) and resetting the FSM upon detection

DETAILED DESCRIPTION The aim of the present invention is to eliminate or substantially reduce the disadvantages described above in known types of FSM by providing a finite-state machine for reliable computing and adjustment systems which eliminates the use of a watchdog timer.
Within the scope of the above described aim, an object of the present invention is to provide a finite-state machine which reduces circuital and user program complexity.
Another object of the present invention is to provide a finite-state machine which substantially eliminates the possibility of any abnormal behavior due to the assuming of an undefined state on the part of said machine.
A further object of the present invention is to provide a finite-state machine which eliminates the possibility of the persistence of an abnormal behavior, detecting the undefined state in any situation.
Not the least object is to provide a finite-state machine which interrupts its operating cycle and/or the operating cycle of the entire system which comprises it if an undefined state is reached.
Not the least object of the present invention is to provide a finite-state machine which is relatively easy to implement and at competitive costs.
This aim, these objects and others which will become apparent hereinafter are achieved by a finite-state machine for reliable computing and adjustment systems according to the invention, comprising a combinatorial logic connected to a state memory by means of connections which carry future state signals and of connections which carry current state signals, said combinatorial logic comprising input terminals for input signals which are external to said finite-state machine and output terminals for output signals generated by said combinatorial logic, characterized in that it comprises means suitable for comparing said future state signals to at least one reference level and for setting an error signal toward means for resetting said finite-state machine.