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Details
Inventors: Providenza, John R.; Boekelheide, Lee;
Assignee: Network Computing Devices, Inc. (Mountain View, CA)
Primary Examiner: Shaw; Dale M.
Assistant Examiner: Tung; Kee M.
Attorney, Agent or Firm: Dellett and Walters

The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.

DETAILED DESCRIPTION According to the present invention in a particular embodiment thereof, raster operations are analyzed before they are actually performed to eliminate unnecessary logic operations and data transfers.
The present invention reduces the number of required clock periods by analyzing the logic relationship between the source and destination operands prior to fetching either operand from memory.
If the result of the raster operation can be determined without actually using the value of either or both of the operands, the reading of unnecessary values can be eliminated.
The new destination result can then be loaded into the address location of the previous destination operand.
In addition, if the raster operation will have no effect on the existing destination operand, the write operation is canceled to reduce the number of memory cycles.
To generate the desired image more effectively, a data pattern is often used to fill areas in a graphic display.
Thus, a pattern operand is employed along with source and destination operands in the raster operation.
In a modification of the present invention, the logical relationship between pattern, source and destination operands is analyzed.
It is possible to preview the effect that the pattern operand will have on the destination value prior to performing the entire raster operation and thus the number of clock cycles required to perform a raster operation involving a pattern operand can also be reduced.
According to another modification, a control signal can be sent to the destination memory operand address instead of actually writing a new destination value into memory.
When special bitblt memory devices are used, the memory control signal can be sent to the image memory address, commanding it to perform certain primitive binary operations.
These binary operations modify the destination operand in such a way as to produce a value equal to the new destination value as would have occurred from writing the result of the raster operation back into memory in the usual manner



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