Charge domain vector-matrix product processing system

DETAILED DESCRIPTION The present invention is an improved charge domain vector-matrix product network for generating the signals representative of the product of an N-element vector and an N.
times.
K element matrix.
The network includes a charge coupled device (CCD) N-stage tapped delay line, an N.
times.
K M-bit digital parallel shift register memory device, N M-bit charge domain digital-analog multipliers, a charge summing device and a controller.
In the preferred form of the invention, the shift register memory device is a charge domain device, but in other forms of the invention, different types may be used, such as CMOS.
The tapped delay line is adapted to establish a succession of N charge packets therein in response to a succession of N applied input signals, where each packet has a magnitude corresponding to one of the element of the vector.
In the delay line, the charge packets are shifted from stage-to-stage along said delay line as the vector data is applied to the product network.
The delay line includes N floating gate sensing electrodes, each overlying one of the stages of the line and being adapted to provide a potential representative of the magnitude of a charge package currently within the underlying stage.
The digital parallel shift register memory device is adapted to storing N.
times.
K M-bit words, where each of the words is representative of the value of a corresponding element of the matrix.
In the preferred form, the shift register memory device includes K stages in a stack configuration, each stage being adapted to store N M-bit words.
The shift register memory device is responsive to an applied shift signal to selectively shifting the stored words from stage-to-stage from the input stage to the output stage of the stack.
The digital-analog multipliers each an analog input port and a digital input port, and provide a charge packet having a magnitude proportional to the product of a potential applied to the analog input port and an M-bit digital signal applied to the digital input port