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Circuit to perform a linear transformation on a digital signal
| Details |
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Inventors: Jutand, Francis; Demassieux, Nicolas; Dana, Michel;
Assignee:
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt
A circuit which performs a linear transformation on a digital signal. A linear transformation is defined by a graph whose nodes represent operations of addition or subtraction and the branches operations of multiplication by a determined coefficient. According to the invention, the circuit comprises a multiplier for each branch, this multiplier being wired according to the value of the determined coefficient of said branch, and an adder for each node, each adder being wired according to the nature of the operation, addition or subtraction, associated with said node. |
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DETAILED DESCRIPTION The object of the invention is to eliminate the drawbacks, particularly the low performance to price ratio, of the circuits according to the prior art.
This object is attained by a circuit for performing a linear transformation whose architecture is traced on that of the graph of the transformation.
In opposition to the known circuits in which the multipliers and the adders are standard circuits, able to multiply or add any two operands, in the circuit of the invention dedicated adders and multipliers are used.
More specifically, a specific multiplier corresponds to each branch of the graph of the transformation, and likewise a specific adder corresponds to each node of the graph of the transformation.
Thus, each multiplier must multiply two operands one of which is fixed and represents the weight of the branch of the associated graph.
Also, each adder is designed to perform only a single operation of addition or subtraction.
The invention therefore has as its object a circuit to perform a linear transformation on a digital signal composed of N samples, where N is a whole number, said circuit comprising a series of stages performing operations of addition and/or multiplication along a determined linear transformation graph, said graph comprising branches each representing an operation of multiplication between a variable operand and a determined coefficient, and nodes each representing an addition or a subtraction between two variable operands, said circuit being characterized in that it comprises a multiplier associated with each branch, this multiplier being wired according to the value of the determined coefficient associated with the branch, and an adder for each node, each adder being wired according to the nature of the operation, addition or substraction, associated with this node.
Preferably, the circuit of the invention is made in the form of a single integrated circuit.
The circuit of the invention exhibits in particular the advantage, compared with known circuits, of a superior computing power thanks to the parallelism between its architecture and the structure of the graph of the linear transformation that it performs
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