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Compiler for performing incremental live variable analysis for data-parallel programs
| Details |
Inventors: Sistare, Steven J.; Frankel, James L.;
Assignee: Thinking Machines Corporation (Cambridge, MA)
Primary Examiner: Kriess; Kevin A.
Assistant Examiner:
Attorney, Agent or Firm: Sterne, Kessler, Goldstein & Fox
A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises an optimizer which optimizes the compiled code. In optimizing the compiled code, the optimizer performs live variable analysis. With regard to performing live variable analysis, the optimizer of the present invention is adapted for use with data parallel languages. Additionally, the optimizer is computationally efficient at compile time. Further, the optimizer operates in an incremental manner. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1.
Hardware and Software Environment of the Present Invention The present invention is directed to a software compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer.
In this patent document, the terms "computer program" and "source code" are used interchangeably.
In a preferred environment of the present invention, the data parallel computer is one manufactured by Thinking Machines Corporation, such as the Connection Machine.
RTM.
Model CM1.
TM.
, CM2.
TM.
and CM5.
TM.
Supercomputers.
These and other preferred environments of the present invention are described in U.
S.
Pat.
No.
4,589,400 to Hillis, U.
S.
Pat.
No.
4,984,235 to Hillis et al.
, and U.
S.
patent application Ser.
No.
07/042,761, entitled "Method and Apparatus for Simulating M-Dimensional Connection Networks in an N-Dimensional Network Where M is Less Than N", filed Apr.
27, 1987, by Hillis, all of which were cited above.
Specifically, U.
S.
Pat.
No.
4,589,400 describes a massively-parallel computer, including one embodiment of processors and router, with which the present invention can be used.
U.
S.
Pat.
No.
4,984,235 describes a massively-parallel computer, including a second embodiment of processors.
U.
S.
patent application Ser.
No.
07/042,761, entitled "Method and Apparatus for Simulating M-Dimensional Connection Networks in an N-Dimensional Network Where M is Less Than N", describes, in a massively parallel computer including processor chips interconnected by a hypercube, an arrangement for emulating the 2-, 3-, or higher dimensional nearest-neighbor communication network ("NEWS") between chips using the hypercube wires.
The computer program is written in a high level language (HLL).
A preferred HLL is C* (pronounced "see star").
C* is based on Standard C and is extended to support parallel instructions and parallel data types.
The C* language is described in the Thinking Machines Corporation publication C* Programming Guide (Version 6
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