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Data access in a processor
| Details |
Inventors: Barlow, Stephen; Ramsdale, Timothy; Swann, Robert; Bailey, Nel; Plowman, David;
Assignee: Broadcom Corporation (Irvine, CA)
Primary Examiner: Chace; Christian P.
Assistant Examiner:
Attorney, Agent or Firm: McAndrews, Held & Malloy
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array. |
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DETAILED DESCRIPTION What is claimed is: 1.
A data processor comprising: a register memory comprising an array of M.
times.
N memory cells, each cell addressable using an instruction specifying a pair of coordinates (I, J), wherein I corresponds to a first modified coordinate if I is greater than M, and wherein J corresponds to a second modified coordinate if J is greater than N.
2.
The data processor in claim 1, wherein the first modified coordinate is equal to (I MOD M).
3.
The data processor in claim 1, wherein the first modified coordinate is equal to M.
4.
The data processor in claim 1, wherein the second modified coordinate is equal to (J MOD N).
5.
The data processor in claim 1, wherein the second modified coordinate is equal to N.
6.
The data processor in claim 1, comprising: a processing unit for executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells using: a first instruction part specifying the pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell.
7.
The data processor in claim 6, wherein the register memory and the processing unit are arranged on the same integrated circuit.
8.
The data processor in claim 6, wherein the wherein the processing unit comprises a graphics processor.
9.
The data processor in claim 1, wherein each cell of the array stores a plurality of bits.
10.
The data processor in claim 1, wherein the register memory comprises a memory access port arranged to: receive the instruction that identifies a plurality of cells using a first instruction part specifying the pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; interpret the instruction to identify the plurality of cells; and return to the data processor the contents of those cells
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