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Method and apparatus for uniform and efficient handling of multiple precise events in a processor by including event commands in the instruction set
| Details |
Inventors: Fernando, John Susantha; Whalen, Shaun Patrick;
Assignee: Lucent Technologies Inc. (Murray Hill, NJ)
Primary Examiner: Lall; Parshotam S.
Assistant Examiner: Vu; Viet
Attorney, Agent or Firm:
An integrated circuit having a digital processor, a decode stage for decoding an instruction from the instruction set, an execute stage coupled to the decode stage for executing the instruction, and event logic coupled to the decode stage operable to provide an event commands to the decode stage to override the instruction. In one embodiment, an integrated circuit having a pipelined processor handles multiple precise events through the decode stage and execute stage through a process which includes the steps of detecting a plurality of events and issuing an event command, selecting a highest priority event from said the of events, providing an event vector and a link address for the highest priority event, and allowing the event vector and the link to be modified for a higher priority event until the event command is issued to the execute stage. |
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DETAILED DESCRIPTION The present invention is directed to a method and apparatus for handling multiple events in a precise manner.
To attain this, the present invention provides an integrated circuit having a digital processor, a decode stage for decoding an instruction from the instruction set, an execute stage coupled to the decode stage for executing the instruction, and event logic coupled to the decode stage operable to provide a plurality of different event commands to the decode stage to override the instruction.
By providing the ability to override the instruction, and thus exploit the flow control used for instruction processing, the digital processor is operable to handle multiple precise events in a low cost manner.
Consequently, the invention also provides a method for handling multiple precise events in a pipelined processor having a decode stage and execute stage which includes the steps of detecting a plurality of events and issuing an event command, selecting a highest priority event, providing an event vector and a link address for the highest priority event, and allowing the event vector and the link to be modified for a higher priority event until the event command is issued to the execute stage.
Thus, the present invention overcomes, to a large extent, the limitations associated with the prior art.
The invention provides a method and apparatus for a processor to handle multiple events precisely in a uniform and efficient manner.
This is done by including event commands which are interpreted like fetched (normal) instructions by the processor.
They may be considered as an extension to the instruction set.
The event commands are not available to the programmer and are issued only by the logic associated with processing events.
The uniformity and efficiency allows the processor to provide fast interrupt processing and single stepping, key attributes in embedded applications, at very low cost.
All events including reset (a basic event), interrupts, and single stepping (a complex event) are sequenced in a uniform manner by a simple finite state machine in the event logic that issues event commands to the decoder
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