Method and apparatus for verifying timing rules for an integrated circuit design

DETAILED DESCRIPTION It is the object of the present invention to provide a method and apparatus for automatic verification of timing rules for an integrated circuit design.
According to the invention, a method of designing an integrated circuit is provided which includes the steps of selecting a plurality of logic blocks to be included in a circuit, and carrying out a timing analysis on the circuit utilizing timing rules verified by 1) generating a timing rule for each of the plurality of logic blocks, and 2) checking the generated timing rules by comparing a timing rule associated with a particular logic block against a synthesized model of the particular logic block to determine timing relationships in the model that are not included in the particular timing rule and timing relationships in the particular timing rule that are not present in the model.
The present invention also includes a computer implemented method implementing the method steps set forth above.
The present invention provides the advantage of a systematic and automatic verification of timing rules utilized in designing an integrated circuit.
The present invention provides the advantage of eliminating the errors caused by automatic program or hand checking or verification of timing rules.