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Logic equation fault analyzer
What is claimed is: 1. A computer system including: A) a plurality of system modules, each of said system modules including means for sensing the occurrence of a ...
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Methods and test platforms for developing an application-specific integrated circuit
What is claimed is: 1. A method for developing a programmed ASIC integrated circuit which includes a signal processor core, a RAM memory and a ROM memory for management ...
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Method for testing reflection LCD projector and display panel pixel area thereof
Accordingly, it is the object of the present invention to provide a highly reliable and efficient testing method for a CMOS silicon wafer LCD in a reflection-type LCD ...
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Audio sample tracker
Briefly, and in general terms, the present invention provides a system for minimizing the error between a future state of the system after a delay and the predicted ...
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Optical proximity correction system
OF THE INVENTION Referring now to FIG. 14, there is illustrated a simplified procedure for mask OPC according to a first embodiment of the present invention. When ...
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Modifying a design layer of an integrated circuit using overlying and underlying design layers
The problems outlined above are in large part solved by the proximity correction technique hereof in which a design layer of an integrated circuit is altered by spatial ...
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Systematic skew reduction through buffer resizing
The present invention addresses the foregoing problems by systematically aligning delay ranges at different levels of a tree-shaped distribution network. Thus, in one ...
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Systematic approach for regularity extraction
1. Overview The invention includes a general approach to extract functional regularity for circuits (and in particular datapath circuits) from high level behavioral or ...
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Method for designing semiconductor integrated circuit
An object of the present invention is eliminating redundant registers as many as possible while taking the delay into account from the layout phase on such that chip ...
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Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
A layout parasitic extraction system is disclosed. The system may be coupled with layout network connectivity extraction (NCE) or layout versus schematic checker (LVS) ...
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