Spread-spectrum transceiver
I claim: 1. A signal comprising a set of binary spreading-code sequences, said set of binary spreading-code sequences being produced by a process of simultaneously: a) combining contents of a single s... Read More
Inventors: Rice, Bart F.;, Assignee: Lockheed Martin Corporation (Bethesda, MD) |
Methods and system for message resource pool with asynchronous and synchronous modes of operation
The particulars shown herein are by way of example and for purposes of illustrative discussion of the embodiments of the present invention. The description taken with the drawings make it apparent to... Read More
Inventors: Coffman, Jerrie L.; Hefty, Mark S.; Tillier, Fabian S.;, Assignee: Intel Corporation (Santa Clara, CA) |
Spread spectrum communication system
What is claimed is: 1. A spread spectrum communication system having predetermined pilot symbols in each of a plurality of physical channels, each of said physical channels being adapted to carry a si... Read More
Inventors: Ono, Shigeru;, Assignee: NEC Corporation (Tokyo, JP) |
Radix converter utilizing automata
The present invention overcomes the aforedescribed disadvantages of prior art radix converters by utilizing one or a plurality of identical modular logic circuits or automata where the plurality of au... Read More
Inventors: Lanning, Walter C.;, Assignee: Sperry Rand Corporation (New York, NY) |
Navigation of aircraft by correlation
I claim: 1. In a method of navigation and aerial guidance under utilization of elevational data correlation, wherein a correlator compares terrain specific elevational reference data, with actually ac... Read More
Inventors: Lerche, Horst-Dieter;, Assignee: MBB GmbH (Bremen, DE) |
Logarithmic data compression
Accordingly, it is an object of the present invention to provide an improved logarithmic data compression apparatus. It is a further object of the invention to provide an improved method of logarithmi... Read More
Inventors: Marchant, Jeffrey D.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Fixed reference shift keying modulation for mobile radio telecommunications
OF THE INVENTION AND A PREFERRED EMBODIMENT A transmitter sends out a phase modulated carrier wave and a reference tone signal which is within the coherence band assigned for each carrier wave. The t... Read More
Inventors: Mammone, Richard J.; Farrell, Kevin; Freeman, Brian;, Assignee: Rutgers University (Piscataway, NJ) |
Charge domain vector-matrix product processing system
The present invention is an improved charge domain vector-matrix product network for generating the signals representative of the product of an N-element vector and an N.times.K element matrix. The ne... Read More
Inventors: Chiang, Alice M.;, Assignee: Massachusetts Institute of Technology (Cambridge, MA) |
Bipolar transistor with particular base structure
The present invention was made in order to solve the foregoing problems, and its object is to reduce the parasitic capacitance between the base and the collector in the bipolar transistor. A further o... Read More
Inventors: Imai, Kiyotaka;, Assignee: NEC Corporation (Tokyo, JP) |
Method and apparatus for extracting parameters for an electrical structure
OF THE PREFERRED EMBODIMENT The present invention provides for parameter extraction for an electrical structure. This parameter extraction is based on a definition of network parameters in which mode... Read More
Inventors: Stengel, Robert E..; Bockelman, David E.; Zhao, Lei;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Automatic performing system capable of detection and correction of errors in performance information
Wherefore, an object of this invention is to provide an automatic performing system in which an error in the transmission of performance information is corrected by transmitting and receiving the perf... Read More
Inventors: Kondo, Tetsusai; Matsui, Haruhiko;, Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho (Hamamatsu, JP) |
System for determining the operations of an integrated circuit and processor for use therein
A first embodiment of the present invention is shown in FIG. 2. The system comprises a translator 2 which receives information supplied by the manufacturer concerning information such as the pin name... Read More
Inventors: Foster, Paul C.;, Assignee: GenRad Inc. (Concord, MA) |
Logic equation fault analyzer
What is claimed is: 1. A computer system including: A) a plurality of system modules, each of said system modules including means for sensing the occurrence of a plurality of module faults and for pro... Read More
Inventors: Lipton, Arnold S.;, Assignee: Bull HN Information Systems Inc. (Billerica, MA) |
Methods and test platforms for developing an application-specific integrated circuit
What is claimed is: 1. A method for developing a programmed ASIC integrated circuit which includes a signal processor core, a RAM memory and a ROM memory for management and processing programs, and in... Read More
Inventors: Bona, Mariano; Comte, Pierre-Albert; Pham-Minh, Duc;, Assignee: SGS-Thomson Microelectronics, S.A. (Gentilly Cedex, FR) |
Method for testing reflection LCD projector and display panel pixel area thereof
Accordingly, it is the object of the present invention to provide a highly reliable and efficient testing method for a CMOS silicon wafer LCD in a reflection-type LCD projector for the purpose of mass... Read More
Inventors: Ho, Yung-Yuan; Chang, Chia-Yuan; Tu, Nang-Ping;, Assignee: Industrial Technology Research Institute (Hsinchu, TW) |
Audio sample tracker
Briefly, and in general terms, the present invention provides a system for minimizing the error between a future state of the system after a delay and the predicted value of the input at that future t... Read More
Inventors: Oliver, Richard J.; Barnes, Casper William;, Assignee: Sony Pictures Entertainment, Inc. (Culver City, CA) |
Optical proximity correction system
OF THE INVENTION Referring now to FIG. 14, there is illustrated a simplified procedure for mask OPC according to a first embodiment of the present invention. When pattern data that is an object of co... Read More
Inventors: Yamamoto, Kazuko; Miyama, Sachiko; Koyama, Kiyomi; Inoue, Soichi;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Modifying a design layer of an integrated circuit using overlying and underlying design layers
The problems outlined above are in large part solved by the proximity correction technique hereof in which a design layer of an integrated circuit is altered by spatial definition using underlying and... Read More
Inventors: Nistler, John L.; Hause, Frederick N.; Etter, Phillip J.;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Systematic skew reduction through buffer resizing
The present invention addresses the foregoing problems by systematically aligning delay ranges at different levels of a tree-shaped distribution network. Thus, in one aspect the invention is directed ... Read More
Inventors: Chan, Chun; Yi, Bing;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Systematic approach for regularity extraction
1. Overview The invention includes a general approach to extract functional regularity for circuits (and in particular datapath circuits) from high level behavioral or structural descriptions, such a... Read More
Inventors: Chowdhary, Amit; Kale, Sudhakar S. J.; Saripella, Phani K.; Sehgal, Naresh K.; Gupta, Rajesh K.;, Assignee: Intel Corporation (Santa Clara, CA) |
Method for designing semiconductor integrated circuit
An object of the present invention is eliminating redundant registers as many as possible while taking the delay into account from the layout phase on such that chip area and power needed by a semicon... Read More
Inventors: Kurokawa, Keiichi; Toyonaga, Masahiko; Ishibashi, Noriko;, Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP) |
Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
A layout parasitic extraction system is disclosed. The system may be coupled with layout network connectivity extraction (NCE) or layout versus schematic checker (LVS) to allow net-by-net layout paras... Read More
Inventors: Ho, William Wai Yan;, Assignee: Synopsys, Inc. (Mountain View, CA) |
Method for channel routing, and apparatus
OF THE PREFERRED EMBODIMENT It is an advantage of the present invention, that it can be used to solve a number of different technical tasks. The present invention will be illustrated using terms defi... Read More
Inventors: Marchenko, Alexander M.; Plis, Andrey P.; Sotnikov, Mikhail A.; McGuinness, Patrick;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Method for assessing the reliability of interconnects
What is claimed is: 1. A method for testing interconnect structures, comprising: forming a plurality of interconnects, each of the interconnects having two ends with a contact and a reservoir located ... Read More
Inventors: Hau-Riege, Christine; Marathe, Amit;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Partitioning and reordering methods for static test sequence compaction of sequential circuits
The present invention included methods of compacting a sequential circuit test vector set by partitioning faults into hard and easy faults, re-ordering vectors in a test set and a combination of parti... Read More
Inventors: Chakradhar, Srimat; Hsiao, Michael S.;, Assignee: NEC USA Inc. (Princeton, NH) |
Worst case design parameter extraction for logic technologies
The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a fr... Read More
Inventors: Krivokapic, Zoran; Heavlin, William D.;, Assignee: Advanced Micro Devices (Sunnyvale, CA) |
Fusible resistor
It is the object of the present invention to provide a fusible resistor which meets all of these requirements. The fusible resistor according to this invention is comprised of an elongated nichrome fi... Read More
Inventors: Ozawa, Juichiro;, Assignee: |
Resistor insertion fuse
What I claim is: 1. A fuse for use in a relatively high voltage circuit comprising: a first conductor element comprising a terminal at one end of said fuse; a second conductor element comprising a ter... Read More
Inventors: Duenke, Clarence G.;, Assignee: Warco, Inc. (Marthasville, MO) |
Performance groups-based fast simulated annealing for improving speed and quality of VLSI circuit placement
The object of this invention is to obviate the above drawbacks in the prior art and improve the speed of VLSI circuit placement by reducing the computational time required. Another object of the inven... Read More
Inventors: Rao, Prahlada B; Patil, Srinivasa R;, Assignee: International Business Machines Corporation (Armonk, NY) |
Method for selecting propagation elements for magnetic bubble memory
A method is described for selecting propagation elements for a magnetic bubble memory which generally includes an epitaxial layer in which magnetic bubbles are propagated and permalloy propagation ele... Read More
Inventors: Washburn, Hudson A.;, Assignee: Intel Corporation (Santa Clara, CA) |
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