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Battery-state-monitoring-circuit

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Battery state monitoring circuit

Details

Inventors: Yokota, Hiroyasu; Sakurai, Atsushi;
Assignee: Seiko Instruments Inc. (Chiba, JP)
Primary Examiner: Tibbits; Pia
Assistant Examiner:
Attorney, Agent or Firm: Adams & Wilks

In a battery state monitoring circuit and a battery device using the same, even if a charge inhibiting signal is inputted to a microcomputer control terminal, a lock mode is prevented from occurring in which both a charge control transistor and a discharge control transistor are turned OFF and a battery voltage can not be supplied to a load. A circuit is structured such that even if the charge inhibiting signal is inputted to the microcomputer control terminal, in the case where the overcurrent voltage detection terminal comes to have the overcurrent detection voltage, the charge inhibiting signal of the microcomputer control terminal is cancelled.

DETAILED DESCRIPTION In order to solve the foregoing problem, according to the present invention, a circuit is added to cancel a charge inhibiting signal of the CTL terminal 13A in a case where the VMP terminal 12A comes to have an overcurrent detection voltage when the charge inhibiting signal is input to the CTL terminal 13A, whereby a lock mode is prevented from occurring in which both the charge control transistor 14A and the discharge control transistor 16A are turned OFF and a battery voltage can not be supplied to a load.
The present invention is constructed such that there is added a circuit for canceling the charge inhibiting signal of the CTL terminal 13A in the case where the VMP terminal 12A comes to have the overcurrent detection voltage while the charge inhibiting signal is being input to the CTL terminal 13A, in a battery state monitoring circuit.

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