Clock control circuits, systems and methods

DETAILED DESCRIPTION Generally, and in one form of the present invention, a microprocessor device includes a central processing unit having a clock input, a clock generator of clock pulses, a logic circuit having an output to supply a clock control signal, and a clock gate fed by the clock pulses and having a clock gate output coupled to the clock input of the central processing unit.
The clock gate responds to the clock control signal to prevent said clock pulses from reaching the central processing unit within one clock cycle of a change in said clock control signal.
In another form of the present invention a clock control circuit has a first logic circuit responsive to a mask clock input, a suspend input and a resume input, and a further interrupt override input, to supply a CPU core suspend control output; and a second logic circuit responsive to an enabling register bit, at least one interrupt input, and a clock signal to supply the interrupt override input to lift CPU core suspend when the interrupt occurs.
Other devices, systems and methods are also claimed.