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| Bandgap reference circuit |
| In accordance with the present invention, a self-starting bandgap reference circuit is provided. "S... |
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| Battery charger where the charge current rate is set by a switch modulated with a variable duty cycle |
| To address the above-discussed deficiencies of the prior art, the present invention provides, for ... |
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| Plural comparator indicator of battery voltage |
| What I claim is: 1. A battery charge capacity indicator for providing an indication of charge ... |
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| Charge status indicator |
| This object is accomplished by a circuit arrangement for indicating the charge status of a battery ... |
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| Method of determining and displaying battery charge status |
| OF EMBODIMENTS Referring first to FIG. 1 of the drawings, a load 2 is concerned to a battery (... |
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| Status indicator for battery charger |
| What is claimed is: 1. Apparatus for indicating multiple operating states of a battery charger ... |
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| Method of and apparatus for setting battery alarm voltage in battery management server |
| It is an object of the present invention to solve at least the problems in the conventional ... |
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Hardware modeling system and method of use
| Details |
Inventors: Read, Andrew J.; Papamarcos, Mark S.; Heideman, Wayne P.; Mardjuki, Robert K.; Couch, Robert K.; Jaeger, Peter R.; Kappauf, William F.; Widdoes, Jr., Lawrence C.; Scheffer, Louis K.;
Assignee: Synopsys, Inc. (Mountain View, CA)
Primary Examiner: Ramirez; Ellis B.
Assistant Examiner:
Attorney, Agent or Firm: Haverstock & Associates
An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system. |
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DETAILED DESCRIPTION The present invention is an improved hardware modeling system and method of use.
The hardware modeling system ("HMS") of the present invention is adaptable for connection to a host computer, which includes a simulator, and is supported by software appropriate for communicating with the HMS.
In fact, the HMS is capable of connecting to, and communicating with, a variety of host computers including a variety of simulators, in particular including conventional digital logic and fault simulators.
The host computers are conventional electronic design workstations; the software that supports their use with the HMS is novel.
The host computer and the HMS are preferably connected by a local-area network over which information is transmitted bi-directionally between the two systems.
Multiple HMSs can be networked with, and concurrently shared by, multiple host computers running multiple different simulators.
The HMS of the present invention provides hardware models of standard ICs, ASICs, and electronic subsystems.
The HMS has a number of applications.
Some of the major ones are as follows: 1) modeling standard off-the-shelf ICs, including static and dynamic ICs and VLSI ICs, in simulation of an electronic system design; 2) modeling custom static and dynamic ICs (ASICs) in simulation of an electronic system design; 3) modeling electronic subsystems and PC boards in simulation; 4) debugging embedded system software and microcode using a simulated prototype; 5) examining the behavior of existing physical standard devices and ASICs; 6) verifying the functional behavior and timing of ASIC prototypes; and 7) generating and capturing standard-device, ASIC, and PC-board test vectors during simulation.
In order to better understand the present invention, it is useful to briefly describe the general overall operation of the HMS as it is used by a typical simulator.
When an electronic circuit is being simulated by a digital simulator including software simulation models of some circuit components, the simulator repeatedly "evaluates" the software simulation models of the components within the circuit
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Electrical and Wave 
