Power control apparatus and method for a body implantable medical device

DETAILED DESCRIPTION The present invention has certain objects.
That is, various embodiments of the present invention provide solutions to one or more problems existing in the prior art with respect to digital logic circuitry in general, and digital logic circuitry used in implantable medical devices in particular.
Such problems include, for example, high power consumption and, in particular, high static power consumption, the present inability to selectively apply power and remove power to and from designated sections of digital logic circuitry without adversely affecting the functionality of the circuitry, and the present inability to exploit a low voltage threshold IC fabrication process that does not result in increased static power consumption for logic devices intended to operate at relatively low switching frequencies.
Various embodiments of the present invention have the object of solving at least one of the foregoing problems.
While some systems have been able to solve the general problem of reducing dynamic power consumption in digital logic devices and circuitry, such approaches have generally resulted in implementations that ignore the problem of increased static power consumption in low speed digital circuits.
It is therefore another object of the present invention to provide an improved apparatus and methodology for controlling power to digital logic circuitry that fulfills at least one of the foregoing objects.
In comparison to known implementations of a power control scheme for digital logic circuitry, various embodiments of the present invention may provide one or more of the following advantages: reducing the average power consumption of digital logic circuitry; reducing the static power consumption of digital logic circuitry; reducing the size of digital circuitry while providing for the reduction of average power consumption and, in particular, static power consumption; and controlling the application and removal of power to and from selected portions of digital logic circuitry to reduce the average power and static power consumed by the circuitry