Serial communication interface system having programmable microcontroller for use in a battery pack

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT System Overview Referring to FIG.
1, a detailed block diagram illustrating microcontroller integrated circuit 10 embodying the present invention is shown.
Microcontroller 10 may take the form of the MTA 140xx/Callisto programmable control integrated circuit manufactured by Microchip Technology Incorporated for use in applications such as battery charging and battery monitoring.
microcontroller 10 is designed for high-volume applications in portable computing, cellular phone, camcorders and other low-cost products where battery charging and monitoring control is desired.
However, it is understood that microcontroller 10 and the present invention is not limited to such applications and may be used in other applications (such as those where it is desired to accurately measure input analog voltages) as will be apparent from the following detailed description.
Microcontroller 10 includes microcontroller core 12 which may take the form of the PIC16C6X/7X microcontroller core also manufactured by Microchip Technology Incorporated ("PIC" is a registered trademark of Microchip Technology Incorporated.
Microcontroller core 12 is an 8-bit reduced instruction set computer (RISC) CPU that includes an 8 level deep stack and multiple internal and external interrupt sources.
The microcontroller core has a Harvard architecture with separate instruction and databuses for allowing a 14-bit wide instruction word with the separate 8-bit wide data.
Moreover, a two-stage instruction pipeline allows for all instructions (35 total) to execute in a single cycle, except for program branches which require two cycles.
Referring to FIG.
2, a graphical diagram illustrating the clock cycle of microprocessor core 12 is shown.
The clock input, either from pin OSC1 or internal oscillator 42, is internally divided into four phases Q1, Q2, Q3 and Q4 whereby the four phases generate a full processor clock cycle.
Two clock cycles are required to complete any instruction whereby an instruction is fetched during one clock cycle and executed during the next clock cycle