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 Synchronizing circuit

Details
Inventors: Willis, Donald H.;
Assignee: Thomson Consumer Electronics, Inc. (Indianapolis, IN)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Ghebretinsae; T.
Attorney, Agent or Firm: Tripoli; Joseph S., Laks; Joseph J., Fried; Harvey D.

A phase locked loop circuit regenerates a synchronizing signal. A first counter counts adjustable and fixed time intervals. A flip/flop generates synchronizing pulses having periods defined by sets of the adjustable and fixed time intervals. A second counter successively measures phase differences between synchronizing pulses and input pulses related to a synchronizing component in a video signal. The phase differences are measured between the ends of the adjustable time intervals in the synchronizing pulses and the input pulses. Each of the phase measurements results in a period correction value for controlling the duration or period of the very next one of the adjustable time intervals. The second counter is reset at the ends of the fixed time intervals. A network defining a loop filter may comprise an accumulator, a first scaler, a summer, and a second scaler for calculating weighted phase difference measurements to define the period correction values. A multiplexer responsive to the synchronizing pulses selects between the period correction values and a constant value as an output value for determining when the first counter is reset.

DETAILED DESCRIPTION The synchronizing circuit disclosed herein according to various inventive arrangements provides low jitter in a regenerated synchronizing signal of one clock period of time, and operates with an accuracy of one clock period, where the clock rate is conveniently 4.
times.
f.
sub.
SC.
The synchronizing circuit is especially appropriate for use in recovering the horizontal synchronizing signal in a subsampled video signal, although the circuit is useful in any context where one clock period accuracy is adequate.
Moreover, the accuracy can be achieved even where the synchronizing signal of the input video is represented by only a single bit, for example the most significant bit.
In accordance with an inventive arrangement, the horizontal synchronizing signal is regenerated with two partial periods or pulse parts, but only one of the partial periods or pulse parts is adjustable; the other partial period or pulse part is constant.
In an NTSC system, for example, the constant partial period or pulse part is set by a time interval of 455 clock periods at 4.
times.
f.
sub.
SC.
This is the value of one-half of the nominal period of a horizontal synchronizing signal.
In accordance with a further inventive arrangement, phase measurements are undertaken between the input pulse corresponding to the synchronizing component of the video signal and only one partial period or pulse part in each regenerated synchronizing pulse.
The trailing edge of the adjustable partial period, for example, can be a phase measurement timing edge.
Each phase measurement results in the calculation of a period correction value for varying the period of the adjustable partial period or pulse part.
In accordance with another inventive arrangement, each calculation of a period correction value related to a phase measurement begins after the end of the fixed partial period or pulse part, and concludes by the end of the adjustable partial period or pulse part.
Therefore, each period correction value controls the very next one of the adjustable time intervals defining the partial periods or pulse parts



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