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| Monolithically integrated semiconductor circuit |
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| Semiconductor device with component circuits under symmetric influence of undesirable turbulence |
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| Memory output circuit |
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| High voltage switching circuit in a nonvolatile memory |
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| Semiconductor memory with segmented word lines |
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| Latch-up control for a CMOS memory with a pumped well |
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| Monolithically integrated semiconductor store |
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Automated safestore stack generation and move in a fault tolerant central processor
| Details |
Inventors: Wilhite, John E.; Lange, Ronald E.;
Assignee: Bull HN Informations Systems Inc. (Billerica, MA)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Chung; Phung My
Attorney, Agent or Firm: Phillips; James H., Solakian; John S.
In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected. Preferably, packing circuitry is included to pack half-word (or shorter) register information into full words in the shadow set to minimize the number of shadow registers and support circuitry required. In the preferred embodiment, during the recovery process, the safestore information in the shadow set is routed through a cache memory which is normally in direct contact with the working register set such that minimum special circuitry is necessary to restore the contents of the working registers. |
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DETAILED DESCRIPTION What is claimed is: 1.
A fault tolerant central processing unit comprising: A) data manipulation circuitry including a plurality of software visible registers, each said software visible register temporarily storing information contents as data is manipulated by said data manipulation circuitry; B) a shadow set of said software visible registers; C) shadowing, packing and validity verification means coupled intermediate said software visible registers and said shadow set for copying the information contents of said plurality of software visible registers, after a data manipulation operation, into said shadow set after the validity of such contents have been verified, said shadowing, packing and validity verification means including combining means for packing information from at least two of said software visible registers, each of which do not exceed half word length, into a single word constituent in said shadow set: and D) resumption of activity means coupled intermediate said shadow set and said software visible registers for replicating the contents of said shadow set in said software visible registers during recovery from a detected fault.
2.
The fault tolerant central processing unit of claim 1 in which said validity verification means further includes: A) error detect means for sensing an occurence of an error which renders invalid the contents of at least one of said software visible registers at the time said error is detected and for issuing an error signal indicating such error occurrence; and B) inhibiting means responsive to the issuance of said error signal to prevent shadowing said plurality of software visible registers into said shadow set.
3.
The fault tolerant central processing unit of claim 2 in which said resumption of activity means further includes a cache memory, the contents of said shadow set being transferred to said software visible registers via said cache memory during recovery from a detected fault.
4.
The fault tolerant central processing unit of claim 1 in which said resumption of activity means further includes a cache memory, the contents of said shadow set being transferred to said software visible registers via said cache memory during recovery from a detected fault
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Fault Detection 
