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Automatic transition charge pump for nonvolatile memories
| Details |
Inventors: Dinh, Khoi Van;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Nelms; David C.
Assistant Examiner: Phan; Trong
Attorney, Agent or Firm: Hill; Daniel D.
Clock frequency and number of stages of a charge pump for nonvolatile memories are automatically adjusted to compensate for lower efficiency due to lower power supply, higher temperature, or weaker process. A low voltage detector will cause the charge pump to increase the charge pump's clock frequency and number of stages when a low voltage is detected, making the charge pump's capability constant over a voltage range. A counter timing programming/erasing time will cause the charge pump clock frequency and number of stages to increase when the programming/erasing time exceeds certain thresholds. This boosts the charge pump's drivability for a weaker process, higher temperature, or aged cells. |
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DETAILED DESCRIPTION Generally, the present invention provides a high voltage charge pump for programming a non-voltage memory that can operate at more than one power supply voltage.
A low voltage detector is used to automatically determine the voltage at which an integrated circuit having the charge pump is operating.
Upon detecting the voltage of the power supply, the low voltage detector determines the number of pump stages required to produce a predetermined high voltage output set, and sets the operating frequency of a clock generator.
The charge pump also includes a timer for controlling the duration of the programming cycles and the magnitude of the output voltage for each of the programming cycles.
After a first programming cycle, subsequent programming cycles use an increased the program voltage to the memory array with a shorten time duration, thus improving reliability of the cells and improving current reliability of the charge pump.
Also, temperature and process variations may be compensated for.
Note that this also applies to erasing cells.
The present invention can be more fully described with reference to FIGS.
1-7.
The terms "assert" and "negate" will be used when referring to the rendering of a signal, status bit, integrated circuit pin, or similar apparatus into its logically true or logically false state, respectively.
If the logically true state is a logic level one, the logically false state will be a logic level zero.
And if the logically true state is a logic level zero, the logically false state will be a logic level one.
FIG.
1 illustrates, in block diagram form, non-volatile memory 10 in accordance with the present invention.
Non-volatile memory 10 includes non-volatile memory array 12, word line driver circuit 14, column logic 16, program/erase/verify control 18, and charge pump 20.
Non-volatile memory array 12 includes a plurality of non-volatile memory cells (not shown) coupled to word lines and bit lines.
Word line driver circuit 14 receives a plurality of row address signals, labeled "ROW ADDRESS", and provides decoded word line signals to non-volatile memory array 12 for selecting one of the word lines
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Fault Detection 
