 Virtual multi-port RAM |
| It is therefore an object of the present invention to provide a multi-port RAM structure which ... |
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| Decoding global drive/boot signals using local predecoders |
| One aspect of the invention comprises a decoding circuit for driving a word line associated with at ... |
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| Semiconductor memory device having even and odd numbered bank memories |
| An object of this ivention is to provide a semiconductor memory device which can simultaneously ... |
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| Semiconductor memory device having split operation and capable of reducing power supply noise |
| An object of the present invention is to provide a semiconductor memory device that effectively ... |
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| Monolithically integrated semiconductor circuit |
| I claim: 1. Monolithically integrated digital semiconductor circuit, comprising an address decoder, ... |
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| Semiconductor device with component circuits under symmetric influence of undesirable turbulence |
| It is therefore an important object of the present invention to provide a semiconductor memory ... |
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| Memory output circuit |
| I claim: 1. In a semiconductor memory, an output circuit comprising: an output transistor series ... |
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| High voltage switching circuit in a nonvolatile memory |
| Accordingly, an object of this invention is to provide a nonvolatile semiconductor memory device ... |
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| Semiconductor memory with segmented word lines |
| It is an object of the present invention to provide a semiconductor memory device, particularly an E... |
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Autonomous N-modular redundant fault tolerant clock system
| Details |
Inventors: Bond, David G.; Hill, Todd; Weis, Paul D.; Woods, John R.;
Assignee: The Boeing Company (Seattle, WA)
Primary Examiner: Safourek; Benedict V.
Assistant Examiner: Chin; Stephen
Attorney, Agent or Firm: Christensen, O'Connor, Johnson & Kindness
A fault tolerant clock system in which synchronization of the clocks continuing to operate after a fault occurs is maintained within a skew limit. The clock system includes a plurality of clock channels (10), each including a clock unit (12) and an isolation port (14). A local clock signal produced by a crystal oscillator (16) is enabled to provide a clock channel output signal while a counter (24) in the clock unit accumulates a predetermined number of local clock pulses. After the predetermined number is reached, the counter disables the clock channel output signal and produces a sync pulse, which is input to a voter block (48). In response to the second sync pulse to be received from each of the clock channels, each voter block produces a load pulse signal that is input to the isolation port of that clock channel. Corresponding isolated load signals are produced by the isolation port and provided to voter blocks (72) in each of the clock units. The voter blocks respond to the second isolated load signal to be received, producing a load enable signal that is input to the counter. Upon receipt of the load enable signal, the counter resumes counting and again enables the clock channel output signal, in synchronization with the other clock channel output signals. Up to N simultaneous faults may be sustained in the clock system, without loss of synchronization in the clock channels that continue to operate properly, so long as 2N+1 clock channels are provided. |
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DETAILED DESCRIPTION In accordance with the present invention, a fault tolerant clock system comprises a first set of fault containment regions that include a plurality of clock units, all of which produce an output time base signal at nominally the same frequency as the other clock units, while operating in a free running mode.
Periodically, the free running mode is interrupted for synchronization of the clock units.
Interconnected with the plurality of clock units are a corresponding plurality of isolation ports, which comprise a second set of fault containment regions.
Each clock unit includes a local oscillator and counter means that are connected to the local oscillator.
The counter means are operative to produce a sync signal at an interval of time that depends on the frequency of the local oscillator.
Also included in each clock unit are first signal select means and second signal select means.
The first signal select means receive the sync signals produced by the counter means of all the clock units and in response to the ith sync signal received, produce a load signal.
Load signals from each clock unit are connected to all of the isolation ports.
In response to the load signals, each isolation port produces a plurality of corresponding isolated load signals.
The second signal select means are connected to receive the corresponding isolated load signals from all of the isolation ports.
Responding to a jth corresponding isolating load signal received, the second signal select means produce an enable signal.
The enable signal in each clock unit is connected to the counter means and causes the counter means to initiate the free running mode at substantially the same time for all of the clock units, so that their output time base signals are substantially synchronized.
Each clock unit further includes switch means that are connected to receive the sync signal for that clock unit.
In response to the sync signal, during synchronization of the clock units, the switch means disable output of the time base signal from the clock unit
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Fault Detection 
