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| Random access memory having a flexible array redundancy scheme |
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| Integrated circuit chip with a wide I/O memory array and redundant data lines |
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| Improved logic cell array using CMOS E.sup.2 PROM cells |
| OF ILLUSTRATIVE EMBODIMENT Referring now to the drawings, FIG. 1 is a schematic block diagram of a ... |
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| DRAM architecture having distributed address decoding and timing control |
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Boundary scan latch configuration for generalized scan designs
| Details |
Inventors: Douskey, Steven Michael; Ganfield, Paul Allen; Young, Daniel Guy;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: De Cady; Albert
Assistant Examiner: Chase; Shelly A
Attorney, Agent or Firm: Xu; Min, Hollingsworth; Mark A.
A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation. |
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DETAILED DESCRIPTION The present invention relates generally to a boundary design of a chip.
More particularly, the present invention relates to a boundary scan latch configuration for generalized scan designs in a single clock chip design.
In one embodiment of the present invention, a boundary circuit includes: at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell.
Still in one embodiment, the internal latch includes a pair of shift register latches controlled by the boundary scan clock input, and a scan/hold control signal.
Further in one embodiment of the present invention, an inverter is connected between the input/output cell and the latch.
Yet in one embodiment of the present invention, the at least one control line controls a function mode.
During a function mode, a signal is sent to/from at least one internal logic unit of the chip for a normal functional operation.
Still in one embodiment of the present invention, the at least one control line controls an INTEST/RUNBIST mode.
During an INTEST/RUNBIST mode, a signal is scanned via the internal latch and sent to at least one internal logic unit of the chip for a test operation.
Additionally in one embodiment of the present invention, the at least one control line controls a LBIST mode.
During a LBIST mode, a signal is scanned in via the internal latch and sent to at least one internal logic unit of the chip for a test operation.
Also, during the LBIST mode, a signal from at least one internal logic unit of the chip can also be scanned out via the internal latch for analysis.
Further in one embodiment of the present invention, the at least one control line controls an EXTEST/WIRETEST mode.
During an EXTEST/WIRETEST mode, a signal is scanned into the internal latch and sent to at least one external logic unit for a test operation.
Also, during an EXTEST/WIRETEST mode, a signal from at least one external logic unit can be received by a receiver of the input/output cell and scanned out via the internal latch for analysis
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Fault Detection 
