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Changing the meaning of a pre-decode bit in a cache memory depending on branch prediction mode
| Details |
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Inventors: Hunt, Douglas B.;
Assignee: Hewlett-Packard Company (Palo Alto, CA)
Primary Examiner: Kim; Kenneth S.
Assistant Examiner:
Attorney, Agent or Firm:
A system for changing the meaning of a pre-decode branch field associated with an instruction in an instruction cache memory of a computer system compatible with multiple branch prediction modes. The system includes a pre-decode unit for decoding instructions from a main memory. The pre-decode unit sets a pre-decode branch field for each branch instruction according to a current branch prediction mode context at the time of pre-decoding. The branch instruction is then inserted into an instruction cache memory. An instruction fetch unit fetches a pre-decoded instruction from the instruction cache and further decodes the instruction. If the instruction is a branch, a branch prediction unit interprets the pre-decode branch field of the branch instruction and computes a predicted branch direction according to the current branch prediction mode and its defined branch prediction mode context. The fetched instruction is inserted into an instruction buffer pending execution by an execution unit. Each of the multiple branch prediction modes result in a different method of predicting a branch instruction direction. In addition, the meaning of a pre-decode branch field differs for each of the defined branch prediction mode contexts defined for each of the multiple branch prediction modes. |
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DETAILED DESCRIPTION OF THE PRESENT INVENTION FIG.
1 shows a block diagram of a portion of a computing system 100 in which the present invention operates.
The computing system 100 includes a main memory 110, a central processing unit (CPU) 150, an instruction cache 120, and a pre-decode unit 130.
The pre-decode unit 130 may reside within the CPU 150 itself, or separately as shown in FIG.
1.
The CPU 150 includes an instruction fetch unit 160, an instruction buffer 170, an execution unit 180, and a branch prediction mode indicator 190.
The instruction fetch unit 160 includes a branch prediction unit 162.
The execution unit 180 also includes an instruction buffer management unit 182.
The branch mode indicator 190 indicates the current branch prediction mode of the currently running process.
The instruction cache 120 of the preferred embodiment is implemented using a high-speed SRAM which has faster access time than the main memory.
The instruction cache 120 comprises a plurality of instruction cache entries, each of which comprise an instruction and associated pre-decode bits.
FIG.
2 illustrates a preferred embodiment for an instruction cache entry 200 in accordance with the present invention.
As shown in FIG.
2, the instruction cache entry 200 includes an instruction field 202 for storing an instruction opcode and associated operands, and a pre-decode control field 204.
The pre-decode control field 204 includes a pre-decode branch subfield 206.
The pre-decode branch sub-field 206 is used, among other things, to indicate whether its associated instruction is a branch instruction.
The number of bits used to implement the pre-decode branch sub-field 206 depends on both the number of branch prediction modes supported by the multiple branch prediction mode compatible computer system and on the type of information provided in a given branch prediction mode context.
In the preferred embodiment, the computer system supports both static prediction mode and dynamic prediction mode, and the context of each mode allows the pre-decode branch subfield 206 to be implemented in only a single bit
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Fault Detection 
