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Checkpointing of register file
| Details |
Inventors: DeLano, Eric;
Assignee: Hewlett-Packard Development Company, L.P. (Houston, TX)
Primary Examiner: Beausoliel; Robert
Assistant Examiner: Chu; Gabriel L.
Attorney, Agent or Firm:
The invention performs an extra read from a register of a register file prior to writing to that register. The data from the extra read is stored in a buffer (e.g., another register file). After a "checkpoint" period, a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint. The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint. The register file of the invention may utilize an extra read port with the register file to perform the extra read. The extra read may occur for every write to the register file; alternatively, the extra read may occur for a subset of the writes to the register file. |
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DETAILED DESCRIPTION The invention in one aspect includes methodology to perform an extra read from a register file prior to writing to that register file.
The data from the extra read is stored in a buffer (e.
g.
, another register file).
After a time period—defined herein as a "checkpoint"—a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint.
Checkpointing of the register file may occur at predetermined time periods, e.
g.
, every 100 cycles.
The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint.
By way of example, the buffer may include twenty registers as compared to one hundred twenty eight registers in the register file.
The register file of the invention may utilize an extra read port with the register file to perform the extra read.
In accord with certain aspects, the invention may perform the extra read for every write to the register file; alternatively, the invention may perform the extra read for a subset of the writes to the register file.
The invention thus protects the processor from inadvertent data errors, such as a corrupted speculative write to the register file.
At the end of each pipeline, often identified by those skilled in the art as the "write-back" stage, the register file is architected; any delay in the write-back stage increases the b ass logic.
Accordingly, the invention preferably architects the register file in norm write-back operations; but a backup copy of the affected register is made within the buffer in case of data errors.
In one aspect, checkpointing occurs after each fixed number of cycles; a larger buffer increases the time slice available for recovery d between checkpoints
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Fault Detection 
