DRAM architecture having distributed address decoding and timing control

DETAILED DESCRIPTION The previously mentioned needs are fulfilled with the present invention.
In one form, a DRAM and method is provided having an architecture with both distributed decoding and timing control.
A plurality of sections of memory cell arrays are coupled to form a plurality of array columns and rows.
Each memory cell array comprises a plurality of columns and rows of DRAM cells.
A first means is positioned adjacent to the sections of memory cell arrays.
The first means receives both an address input and a timing control signal.
The first means provides both a first partial decode signal and a second signal having both decoding and timing control information.
The first partial decode and second signals address a predetermined section of memory cell arrays at a predetermined time.
A second means is coupled to each memory cell array for receiving both the first partial decode signal and the second signal.
The second means further decodes the first partial decode signal and second signal to provide a select signal to activate a predetermined row of DRAM cells within at least one of the arrays.
The second signal to generate critical timing to accurately control when the predetermined row of DRAM cells is activated regardless of inherent clock skew associated with the timing control signal.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.