Dynamic random access memory device having sense amplifier circuit arrays sequentially activated

DETAILED DESCRIPTION It is therefore an important object of the present invention to provide a dynamic random access memory device which is improved in data access speed.
To accomplish these objects, the present invention proposes to sequentially activate sense amplifier circuits.
In accordance with the present invention, there is provided a dynamic random access memory device fabricated on a single semiconductor chip, comprising: a) a memory cell array implemented by a plurality of memory cells respectively storing a plurality of data bits in the form of electric charges; b) a plurality of bit line pairs associated with the memory cell array, and propagating data bits in the form of differential voltage level; c) a plurality of word lines selectively driven to an active level for allowing data bits to be transferred between the plurality of bit line pairs and memory cells selected from the plurality of memory cells; d) a plurality of sense amplifier circuits respectively coupled with the plurality of bit line pairs, and operative to develop the data bits in the form of differential voltage level on the associated bit line pairs upon activation thereof; and e) an activation means provided in association with the plurality of sense amplifier circuits, and operative to respectively activate the plurality of sense amplifier circuits by coupling the plurality of sense amplifier circuits with a constant voltage source.