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Home Fault Detection Dynamic-random-access-memory-device-with-staggered-refresh

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Details
Inventors: Mashiko, Koichiro;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Hecker; Stuart N.
Assistant Examiner: Bowler; Alyssa H.
Attorney, Agent or Firm: Lowe, Price, LeBlanc, Becker & Shur

A dynamic random access memory (DRAM) comprises a divided plurality of memory array blocks. Each memory array block comprises a memory array having memory cells and a sense amplifier. In refresh operation, activating signals for activating each of the sense amplifiers are outputted. The output timings of the activating signals are different from each other, so that each of the sense amplifiers are activated at different timings. Consequently, a peak value of the current consumed by the activation of the sense amplifiers can be reduced.

DETAILED DESCRIPTION One object of the present invention is to reduce a peak value of a current consumed in the DRAM in the refresh operation.
Another object of the present invention is to reduce a peak value of a current consumed by sense amplifiers in the DRAM in the refresh operation.
A further object of the present invention is to minimize degradation of sensitivity of sense amplifiers in the DRAM in the refresh operation.
A still further object of the present invention is to prevent malfunctions of other circuits in the DRAM in the refresh operation.
A still further object of the present invention is to facilitate designing of the memory board which includes the DRAM.
Briefly stated, the present invention comprises a plurality of memory array blocks each comprising a memory array having memory cells and a sense amplifier for amplifying data signals stored in the memory cells; a circuit for detecting external designation of refresh mode; a circuit for outputting an activating signal for activating the sense amplifier; and a circuit for applying at least first and second timing controlled activating signals which are displaced in time to the sense amplifiers in response to the activating signal in the refresh mode.
In operation, when the designation of the refresh mode is detected, generated are at least first and second timing controlled activating signals which are displaced in time from each other.
At least one of the plurality of memory arrays is activated in response to the first timing controlled activating signal and at least another one is activated in response to the second signal.
Since the timing of activation of these sense amplifiers are different from each other, the peak value of the current consumed by the activation of the sense amplifiers can be reduced.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings



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