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System and method for monitoring point identification
OF THE PREFERRED EMBODIMENTS The present invention is directed to an improved system and method for enhancing the performance monitoring capabilities of a ...
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Unit switching apparatus with failure detection
It is an object of the present invention to provide a unit switching apparatus which can set a spare unit with the same setting as that of a faulty current unit within a ...
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Dynamic random access memory device having sense amplifier circuit arrays sequentially activated
It is therefore an important object of the present invention to provide a dynamic random access memory device which is improved in data access speed. To accomplish these ...
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Integrated semiconductor memory with parallel test capability and redundancy method
We claim: 1. An integrated semiconductor memory, comprising: U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), and means ...
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Method and apparatus for testing a connection between digital processing modules, such as in digital printing
We claim: 1. A method of testing a connection between a first module and a second module, the first module and second module being intended to exchange digital ...
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Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
The invention may be implemented in a semiconductor memory integrated circuit by providing response circuitry at the ends of signal lines internal to the memory. E...
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Integrated circuit memory with column voltage holding circuit
An object of the present invention is to make an integrated circuit memory comprising a circuit that can be used to obtain a voltage at the column BL selected for the ...
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Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices
In view of the state of art described, the object of the present invention is to realize a row address decoding and selection circuitry which allows the simultaneous ...
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Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
I claim: 1. A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F.sub.k that is ...
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Standby current detecting circuit for use in a semiconductor memory device and method thereof
Therefore, it is an object of the present invention to provide a standby current detecting circuit and method for detecting where within a semiconductor memory device a ...
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