 Decoding global drive/boot signals using local predecoders |
| One aspect of the invention comprises a decoding circuit for driving a word line associated with at ... |
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| Semiconductor memory device having even and odd numbered bank memories |
| An object of this ivention is to provide a semiconductor memory device which can simultaneously ... |
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| Semiconductor memory device having split operation and capable of reducing power supply noise |
| An object of the present invention is to provide a semiconductor memory device that effectively ... |
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| Monolithically integrated semiconductor circuit |
| I claim: 1. Monolithically integrated digital semiconductor circuit, comprising an address decoder, ... |
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| Semiconductor device with component circuits under symmetric influence of undesirable turbulence |
| It is therefore an important object of the present invention to provide a semiconductor memory ... |
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| Memory output circuit |
| I claim: 1. In a semiconductor memory, an output circuit comprising: an output transistor series ... |
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| High voltage switching circuit in a nonvolatile memory |
| Accordingly, an object of this invention is to provide a nonvolatile semiconductor memory device ... |
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| Semiconductor memory with segmented word lines |
| It is an object of the present invention to provide a semiconductor memory device, particularly an E... |
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| Latch-up control for a CMOS memory with a pumped well |
| An object of the present invention is to provide an improved power-up circuit for a DRAM. Another ... |
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Expandable digital error detection and correction device
| Details |
Inventors: Miller, Michael J.; Chan, Andy P.; Stodieck, Robert W.; Mick, John R.;
Assignee: Integrated Device Technology, Inc. (Santa Clara, CA)
Primary Examiner: Baker; Stephen M.
Assistant Examiner:
Attorney, Agent or Firm: Schatzel; Thomas E.
A pair of similar, 32-bit, error detection and correction devices, including a "lower 32-bit" device (210) and an "upper 32-bit" device (212) are configured as a 64-bit, error detection and correction system. When a (64-bit) word of data is being stored in memory, the lower 32-bit device (210) develops, on an inter-device bus (226), signals representing generation partial check bits. The upper 32-bit device (212) receives the partial check bits (226), and develops signals representing final check bits (236) for storage with the corresponding data word in memory (220 and 234). When a (64-bit) word of data is being retrieved from memory, from signals representing check bits retrieved from memory (222), the lower 32-bit device (210) generates on an inter-device bus (224), signals representing correction partial syndromes. From the correction partial syndromes (224), the upper 32-bit device (212) develops, on another inter-device bus (228), signals representing correction partial check bits; generates full syndromes; and corrects errors in the upper 32-bits of the corresponding retrieved data word (240). From the correction partial check bits (228) the lower 32-bit device (210) (also) generates full syndromes; and corrects errors in the corresponding lower 32-bits of the retrieved data word (230). |
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DETAILED DESCRIPTION What is claimed is: 1.
An error detection and correction device (300) comprising in combination: a first device bus (310); a second device bus (312); a third device bus (318); a fourth device bus (314); a fifth device bus (316); a sixth device bus (320); a first, data, latch means (340) connected to said first device bus (310); a correction check bit generator (342) connected to said first latch means (340); a second, check bit, latch means (346) coupled to said second device bus (312); a first multiplexer means (348) connected to said second device bus (312) and to said second latch means (346); a first gate means (350) connected to said correction check bit generator (342) and to said first multiplexer means (348); a second multiplexer means (352) connected to said correction check bit generator (342), to said first gate means (350), and to said third device bus (318); a first tri-state buffer means (380) connected to said first device bus (310); a second tri-state buffer means (382) connected to said fifth device bus (316); a generation check bit generator (400) connected to said first tri-state buffer means (380); a third multiplexer means (402) connected to said correction check bit generator (342) and to said fourth device bus (314); a second gate means (404) connected to said third multiplexer means (402) and to said generation check bit generator (400); a fourth multiplexer means (406) connected to said second gate means (404), to said generation check bit generator (400), and to said second tri-state buffer means (382); a third gate means (408) connected to said fourth device bus (314) and to said first gate means (350); a fifth multiplexer means (410) connected to said third gate means (408) and to said first gate means (350); a combination of an error decoder, error corrector, and pipe-line latch means (520), the combination coupled to said fifth multiplexer means (410); a third tri-state buffer means (522) connected between said error decoder, error corrector, and pipe-line latch means combination (520) and said sixth device bus (320); a third, data, latch means (560) connected to said sixth device bus (320); and a sixth multiplexer means (562) connected to said error decoder, error corrector, and pipe-line latch means combination (520), to said third latch means (560), and to said first tri-state buffer means (380)
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Fault Detection 
