Hardware instruction scheduler for short execution unit latencies

DETAILED DESCRIPTION In accordance with the present invention an apparatus for scheduling a stream of instructions per cycle of the apparatus includes means for scheduling a stream of instructions for execution by providing each instruction in said stream of instruction with a cycle number indication of when the instruction can be issued by the apparatus and means for storing said stream of instruction and the cycle number of when the instruction can be issued.
With such an arrangement, a scheduler which is suitable for short latency execution cycles is provided.
Since the scheduler schedules instructions before a need arises to issue them, the scheduler can work as fast as is necessary.
Moreover, the scheduler can handle instruction dependancies by scheduling in the same scheduling cycle multiple instructions with such dependencies to issue in different cycles.
The scheduler can also schedule the instructions to issue in a cycle with other instructions for which resources are ready or for which no dependancy is found.
That is, the scheduler is particular well suited for multiple execution machines having fast execution units.
In accordance with a further aspect of the present invention, an apparatus includes means for storing a status bit indication of the availability of data associated with the contents of a plurality of stored register operands and means for determining whether a source register operand of one of said instructions is dependant upon a destination operand of any one of the plurality of instructions preceding said instruction.
The apparatus further includes means for determining for each of said instructions suceeding a current instruction, possible combinations of latencies of said current instruction and preceding ones of said current instruction in a current instruction cycle and a base number of cycles of execution when each operand of said current instruction will have valid data ready, and means for comparing the base number and an earliest possible cycle number value and said latency combinations for each of said instructions, and assigning for each of said instructions the smallest one of said values as an issue cycle number associated with said instruction