Hierarchically managed boundary-scan testable module and method

DETAILED DESCRIPTION OF THE DRAWINGS FIG.
1 is a block diagram of electronic system 10 that accommodates JTAG testing through the use of a hierarchically managed testable module 12.
System 10 includes tester 14 and any number of JTAG components 16 and modules 12.
Tester 14 is a conventional JTAG tester and JTAG components 16 are conventional JTAG components.
Tester 14 drives a conventional JTAG bus, which includes test data in (TDI), test data out (TDO), test mode select (TMS) and test clock (TCK) signals.
Although not shown, a test reset (TRST) signal may be included as well.
Components 16 couple to the JTAG bus in a conventional manner.
In particular, boundary-scan registers 18 of components 16 are coupled in series using TDI inputs and TDO outputs to form a boundary-scan chain driven by and terminated at tester 14.
Module 12 includes at least one master JTAG component 20 and any number of slave JTAG components 22.
Master component 20 and each slave component 22 are physically separated semiconductor die or chips which are electrically interconnected together.
Master component 20 and slave components 22 may be physically mounted together on a common substrate or circuit board or otherwise encapsulated or mounted together.
Master component 20 includes test access port (TAP) controller 24 and related control circuits (not shown), core logic section 30 and boundary-scan register 18 partitioned into an external register 26 and internal register 28.
Master component 20 has TDI input 31 and TDO output 32 accessible from outside module 12.
TMS and TCK inputs to master component 20 are accessible from outside module 12.
Slave components 22 each include a boundary-scan register 18 partitioned into external register 34 and internal register 36.
Control bus 35 is driven by TAP controller 24 of master component 20.
Bus 35 couples to slave components 22 so that boundary-scan registers 18 of slave components 22 are controlled by TAP controller 24 of master component 20.
In particular, boundary-scan registers 18 of slave components 22 are controlled in response to the various JTAG states and JTAG instructions detected and decoded at master component 20