High speed read/modify/write memory system and method

DETAILED DESCRIPTION One form of the present invention is an improvement for a data processing system.
The improvement comprises a memory for storing data elements, a first cache register connected to the memory, and a second cache register connected in parallel with the first cache register.
Each data element has a unique address and includes N data words.
The first register receives from the memory a single data element to be modified.
The second register receives one or more data words to replace corresponding data words in the single data element.
The improvement further comprises means for transferring to the memory the data words from the second cache register together with noncorresponding data words from the first cache register.
Another form of the present invention is a method for overwriting a first data word in a memory by a second data word, wherein each addressable location in the memory holds a data element with N data words.
The method comprises reading the data element which includes the first data word from the memory into a first cache register, simultaneously writing the second data word to a second cache register, and then writing into the main memory the second data word along with all of the words of the data element in the first cache register save the first word.