 Standby current detecting circuit for use in a semiconductor memory device and method thereof |
| Therefore, it is an object of the present invention to provide a standby current detecting circuit ... |
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| Process and device for checking substrate wafers |
| Since a defect counting process, particularly a counting process carried out by an operator, is ... |
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| Synchro-to-digital converter |
| Accordingly, a primary object of the present invention is to provide a synchro-to-digital converter ... |
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| Duty cycle control apparatus |
| What is claimed is: 1. Apparatus for controlling the duty cycle of an input signal having a period, ... |
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| Signal level comparing circuit |
| It is accordingly an object of this invention to provide a signal level comparing circuit which can ... |
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| Circuit arrangement for correcting slip errors in pcm receivers |
| I claim: 1. In a receiver for binary code words including information bits and redundancy bits to ... |
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| Redundant clock system utilizing nonsynchronous oscillators |
| In accordance with the present invention, there is provided a clock system with two nonsynchronized ... |
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Highspeed parallel adder with clocked switching circuits
| Details |
Inventors: Sahoda, Masayuki; Tanaka, Fuminari; Iida, Tetsuya;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner
In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage. |
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DETAILED DESCRIPTION It is an object of the present invention to provide full adder circuits which can constitute a parallel adder circuit arranged to shorten the carry propagation delay time.
It is another object to provide a parallel adder circuit which can shorten the carry propagation delay time.
According to a parallel adder circuit of the invention, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding-stage full adder is connected to the carry input terminal of the succeeding-stage full adder.
The first full adder comprises a first control circuit responsive to an addend input signal and an augend input signal applied to the addend input terminal and augend input terminal for providing a first switch control signal which becomes a first logical level when the addend input signal and augend input signal are equal and which becomes a second logical level when the input signals are not equal, a first input circuit connected to receive the addend and augend input signals to provide a NAND output signal or a NOR output signal of the input signals or an inverted signal of one of the input signals as an output signal, and a first switching circuit having first to fourth inverting type switching means, the first and fourth switching means being arranged to conduct when the first switch control signal from the first control circuit is at the first logical level, the second and third switching means being arranged to conduct when the first switch control signal from the first control circuit is at the second logical level, the first and second switching means being connected to respectively receive a carry inverted input signal from the preceding stage that is applied to the carry input terminal and its inverted signal, and having their outputs connected together to the sum output terminal, and the third and fourth switching means being connected to respectively receive the carry inverted input signal from the preceding stage that is applied to the carry input terminal and the output signal from the first input circuit, and having their outputs connected together to the carry output terminal
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Fault Detection 
