 High voltage switching circuit in a nonvolatile memory |
| Accordingly, an object of this invention is to provide a nonvolatile semiconductor memory device ... |
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| Semiconductor memory with segmented word lines |
| It is an object of the present invention to provide a semiconductor memory device, particularly an E... |
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| Latch-up control for a CMOS memory with a pumped well |
| An object of the present invention is to provide an improved power-up circuit for a DRAM. Another ... |
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| Monolithically integrated semiconductor store |
| An object of the invention is to further reduce the storage space required for a semiconductor ... |
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| Adaptive digital radio communication system |
| An illustrative embodiment of the adaptive digital radio communications system according to the ... |
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| Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder |
| This invention relates to programmable, reconfigurable implementations of Reed-Solomon encoder/... |
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| Optimizing repeaters positioning along interconnects |
| A preferred embodiment of the present invention provides an aspect of interconnect design for ... |
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| Method and apparatus for placing repeaters in a network of an integrated circuit |
| OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used ... |
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Integrated circuit I/O using a high performance bus interface
| Details |
Inventors: Farmwald, Michael; Horowitz, Mark;
Assignee: Rambus, Inc. (Mountain View, CA)
Primary Examiner: Nguyen; Viet Q.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide. |
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DETAILED DESCRIPTION The present invention is designed to provide a high speed, multiplexed bus for communication between processing devices and memory devices and to provide devices adapted for use in the bus system.
The invention can also be used to connect processing devices and other devices, such as I/O interfaces or disk controllers, with or without memory devices on the bus.
The bus consists of a relatively small number of lines connected in parallel to each device on the bus.
The bus carries substantially all address, data and control information needed by devices for communication with other devices on the bus.
In many systems using the present invention, the bus carries almost every signal between every device in the entire system.
There is no need for separate device-select lines since device-select information for each device on the bus is carried over the bus.
There is no need for separate address and data lines because address and data information can be sent over the same lines.
Using the organization described herein, very large addresses (40 bits in the preferred implementation) and large data blocks (1024 bytes) can be sent over a small number of bus lines (8 plus one control line in the preferred implementation).
Virtually all of the signals needed by a computer system can be sent over-the bus.
Persons skilled in the art recognize that certain devices, such as CPUs, may be connected to other signal lines and possibly to independent buses, for example a bus to an independent cache memory, in addition to the bus of this invention.
Certain devices, for example cross-point switches, could be connected to multiple, independent buses of this invention.
In the preferred implementation, memory devices are provided that have no connections other than the bus connections described herein and CPUs are provided that use the bus of this invention as the principal, if not exclusive, connection to memory and to other devices on the bus.
All modern DRAM, SRAM and ROM designs have internal architectures with row (word) and column (bit) lines to efficiently tile a 2-D area
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Fault Detection 
