Integrated semiconductor memory with parallel test capability and redundancy method

DETAILED DESCRIPTION We claim: 1.
An integrated semiconductor memory, comprising: U block groups (GP.
sub.
u=1 .
.
.
U) each having groups of M memory cells (MC) and word lines (WL), and means for simultaneously testing several of said groups of M memory cells (MC) for operation in a test mode, each of said groups of memory cells being disposed along a respective word line (WL) within a respective one of said U block groups (GP.
sub.
u); said testing means being in the form of a parallel test device (PT) associated with said U block groups (GP.
sub.
u=1 .
.
.
U) for writing in and evaluating data to be written into and read out of the semiconductor memory; said parallel test device including means for evaluating data read out in the test mode separately for each of said block groups; and I/O data lines (IO1, IO2, IO3) of the semiconductor memory separately carrying a result of the evaluation for each of said groups of M memory cells (MC).
2.
The integrated semiconductor memory according to claim 1, wherein: each of said block groups (GP.
sub.
u) includes V memory blocks (BK.
sub.
v=1 .
.
.
V) with memory cells (MC) disposed in matrix form along said word lines (WL) and bit lines (BL), a maximum of one memory block (BK.
sub.
v) per block group (GP.
sub.
u) is selected during operation, each of said memory blocks (BKV) includes: a block decoder (BDEC) for selecting a respective memory block from a set of memory blocks (BK.
sub.
1 .
.
.
V) of a block group (GP.
sub.
u) as a function of block addresses (ADBK) supplied to it, the selection being effected by means of a block selection signal (BKSIG), word line decoders (WLDEC) for selecting said word lines (WL) as a function of word line addresses (ADWL) and of the block selection signal (BKSIG), read amplifiers (SA) each being connected to a pair of said bit lines (BL) and a pair of connecting lines, bit switches (BSW) for an optional connection of said pair of connecting lines to one of M pairs of data lines for reading (BKDB-RD) and for writing (BKDB-WR) of a block databus (BKDB), each M bit switches (BSW) being jointly activated as a bit switch block (BKBSW) by a bit group selection signal (BITSIG), a bit group decoder (BITDEC) supplying the bit group selection signals (BITSIG) as output signals and being activated by bit group addresses (ADBIT), at least one bit group decoder (BITDEC) being provided for all of said memory blocks (BK